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ADVANCE APPLICATION NOTE PMC-990639 ISSUE 1
PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
PM7381
FREEDMTM-32A672
FRAME ENGINE AND DATALINK MANAGER 32A672
PROGRAMMER'S GUIDE
PROPRIETARY AND CONFIDENTIAL ADVANCE ISSUE 1: JUNE 1999
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ADVANCE APPLICATION NOTE PMC-990639 ISSUE 1
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CONTENTS 1 INTRODUCTION ...................................................................................... 1 1.1 1.2 1.3 1.4 SCOPE .......................................................................................... 1 TARGET AUDIENCE...................................................................... 1 NUMBERING CONVENTIONS...................................................... 1 REGISTER DESCRIPTION ........................................................... 1 1.4.1 NORMAL MODE REGISTERS ........................................... 2 2 3 REFERENCES ......................................................................................... 3 FREEDM-32A672 OVERVIEW................................................................. 4 3.1 3.2 4 5 FREEDM-32A672 SUMMARY ....................................................... 4 ANY-PHY PACKET INTERFACE .................................................... 6
INTERRUPT ARCHITECTURE ................................................................ 8 CONFIGURING THE SERIAL LINKS ....................................................... 9 5.1 5.2 5.3 5.4 5.5 5.6 CHANNELISED T1/J1 LINKS ........................................................ 9 CHANNELISED E1 LINKS........................................................... 11 UNCHANNELISED LINKS WITH BYTE SYNCHRONIZATION.... 12 UNCHANNELISED LINKS WITHOUT SYNCHRONIZATION ...... 14 8.192 MBPS H-MVIP LINKS........................................................ 16 2.048 MBPS H-MVIP LINKS........................................................ 18
6
CONFIGURING THE ANY-PHY PACKET INTERFACE .......................... 21 6.1 6.2 CONFIGURING THE RECEIVE ANY-PHY PACKET INTERFACE (RAPI672) .................................................................................... 21 CONFIGURING THE TRANSMIT ANY-PHY PACKET INTERFACE (TAPI672) ..................................................................................... 23
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HDLC AND CHANNEL FIFO CONFIGURATION.................................... 26 7.1 7.2 7.3 CONFIGURING THE RHDL672................................................... 26 CONFIGURING THE THDL672 ................................................... 27 PROGRAMMING A CHANNEL FIFO .......................................... 28 7.3.1 RECEIVE CHANNEL FIFO ............................................... 29 7.3.2 TRANSMIT CHANNEL FIFO............................................. 30 7.4 7.5 RHDL672 CHANNEL CONFIGURATION..................................... 31 THDL672 CHANNEL CONFIGURATION ..................................... 34
8
FREEDM-32A672 OPERATIONAL PROCEDURES............................... 40 8.1 8.2 8.3 8.4 8.5 8.6 DEVICE IDENTIFICATION, LOCATION AND SYSTEM RESOURCE ASSIGNMENT ........................................................ 40 RESET......................................................................................... 40 INITIALIZATION ........................................................................... 41 ACTIVATION PROCEDURE......................................................... 41 DEACTIVATION PROCEDURE.................................................... 42 PROVISIONING A CHANNEL ..................................................... 43 8.6.1 RECEIVE CHANNEL PROVISIONING ............................. 43 8.6.2 TRANSMIT CHANNEL PROVISIONING........................... 45 8.7 UNPROVISIONING A CHANNEL ................................................ 48 8.7.1 RECEIVE CHANNEL UNPROVISIONING ........................ 48 8.7.2 TRANSMIT CHANNEL UNPROVISIONING...................... 50 8.8 8.9 8.10 RECEIVE SEQUENCE ................................................................ 53 TRANSMIT SEQUENCE.............................................................. 53 PERFORMANCE COUNTERS .................................................... 54
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8.11 8.12 8.13
LINE LOOPBACK ........................................................................ 56 DIAGNOSTIC LOOPBACK .......................................................... 57 BERT PORT................................................................................. 57
APPENDIX A - REGISTER LEVEL CHANGES................................................ 59 APPENDIX B - NEW NORMAL MODE REGISTERS....................................... 66 APPENDIX C - NON-APPLICABLE NORMAL MODE REGISTERS................ 67 APPENDIX D - NORMAL MODE REGISTER BIT CHANGES ......................... 69
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LIST OF FIGURES FIGURE 1 - FREEDM-32A672 BLOCK DIAGRAM ............................................ 5 FIGURE 2 - CHANNELISED T1/J1 RECEIVE LINK TIMING.............................. 9 FIGURE 3 - CHANNELISED T1/J1 TRANSMIT LINK TIMING ......................... 10 FIGURE 4 - CHANNELISED E1 RECEIVE LINK TIMING ................................ 11 FIGURE 5 - CHANNELISED E1 TRANSMIT LINK TIMING.............................. 11 FIGURE 6 - UNCHANNELISED RECEIVE LINK TIMING WITH BYTE SYNCHRONIZATION ........................................................................................ 13 FIGURE 7 - UNCHANNELISED TRANSMIT LINK TIMING WITH BYTE SYNCHRONIZATION ........................................................................................ 13 FIGURE 8 - UNCHANNELISED RECEIVE LINK TIMING WITHOUT SYNCHRONIZATION ........................................................................................ 14 FIGURE 9 - UNCHANNELISED TRANSMIT LINK TIMING WITHOUT SYNCHRONIZATION ........................................................................................ 15 FIGURE 10 - RECEIVE 8.192 MBPS H-MVIP LINK TIMING ........................... 16 FIGURE 11 - TRANSMIT 8.192 MBPS H-MVIP LINK TIMING......................... 17 FIGURE 12 - RECEIVE 2.048 MBPS H-MVIP LINK TIMING ........................... 19 FIGURE 13 - TRANSMIT 2.048 MBPS H-MVIP LINK TIMING......................... 19 FIGURE 14 - SPECIFYING A CHANNEL FIFO ............................................... 29 FIGURE 15 - EVENT SEQUENCE FOR POLLING OF COUNTERS............... 54 FIGURE 16 - LINE LOOPBACK ....................................................................... 56 FIGURE 17 - DIAGNOSTIC LOOPBACK ......................................................... 57
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1 1.1
INTRODUCTION Scope The FREEDM-32A672 Programmer's Guide is intended to describe the configurable features and operation of a FREEDM-32A672 from a programmer's perspective. This document may not cover all applications of the FREEDM32A672. Please contact a PMC-Sierra Applications Engineer for specific uses not covered in this document. This document is a supplement to the FREEDM-32A672 Longform Datasheet[1]. Both documents should be studied together to interface the FREEDM-32A672 to an embedded processor. In case of a discrepancy between the Programmer's Guide and the Longform Datasheet, the Longform Datasheet shall always be considered correct.
1.2
Target Audience The target audience for this document is programmers who will be writing software to configure and control the FREEDM-32A672. This document has been prepared for readers with some prior knowledge of the HDLC protocol.
1.3
Numbering Conventions The following numbering conventions are used throughout this document: binary decimal hexadecimal 011 1010B, 011 129, 6, 12 0x1FE2, 09FH
1.4
Register Description Unless specified otherwise, FREEDM-32A672 registers are described using the convention REGISTER_NAME (address in FREEDM-32A672). There is only one register space that can be addressed on a FREEDM-32A672, and it consists of the normal mode microprocessor accessible registers.
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1.4.1 Normal Mode Registers Normal mode registers are used to configure, monitor and control the operation of the FREEDM-32A672. Registers must be accessed as 16-bit values with a DWORD aligned address. For all register descriptions, the hexadecimal register number indicates the address in the FREEDM-32A672 when accesses are made using the external microprocessor. A register value is accessed through an external microprocessor, and has the following characteristics: * Writing values into unused register bits has no effect. However, to ensure software compatibility with future versions of the product, unused register bits should be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. Except where noted, all configuration bits that can be written into can also be read back. This allows the processor controlling the FREEDM-32A672 to determine the programming state of the block. Writable normal mode registers are cleared to logic zero upon reset unless otherwise noted. Writing into read-only normal mode register bit locations does not affect FREEDM-32A672 operation unless otherwise noted. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the FREEDM32A672 operates as intended, reserved register bits must only be written with their default values. Similarly, writing to reserved registers should be avoided.
*
* * *
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PM7381 FREEDM-32A672
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REFERENCES 1. PMC-990263, PMC-Sierra, Inc., "Frame Engine and Data Link Manager 32A672" Longform Datasheet, February 1999, Issue 1. 2. PMC-990262, PMC-Sierra, Inc., "Frame Engine and Data Link Manager 32P672" Longform Datasheet, February 1999, Issue 1. 3. PMC-960758, PMC-Sierra, Inc., "Frame Engine and Data Link Manager" Longform Datasheet, May 1998, Issue 5.
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3 3.1
FREEDM-32A672 OVERVIEW FREEDM-32A672 Summary The PM7381 FREEDM-32A672 Frame Engine and Datalink Manager is an advanced data link layer processor that is ideal for applications such as IETF PPP interfaces for routers, TDM switches, Frame Relay switches and multiplexors, ATM switches and multiplexors, Internet/Intranet access equipment, packet-based DSLAM equipment, and Packet over SONET. The FREEDM32A672 implements HDLC processing for a maximum of 672 bi-directional channels. The functional blocks of the FREEDM-32A672 are illustrated in Figure 1. As many as 32 bi-directional serial links can be connected to the FREEDM32A672. These are processed by the Receive Channel Assigner (RCAS672) and Transmit Channel Assigner (TCAS672) blocks. The RCAS672 and TCAS672 can be interfaced to H-MVIP channelised T1/J1/E1, or unchannelised links. , The data stream at each serial port can be assigned to one or more of the FREEDM-32A672 channels. There are as many as 672 receive channels and 672 transmit channels available for assignment to unchannelised links, or to time-slots within a channelised T1/J1/E1 or H-MVIP link. When configured for 2.048 Mbps H-MVIP operation, the FREEDM-32A672 partitions the 32 physical links into 4 logical groups of 8 links. Links in each logical group share a common clock and a common type 0 frame pulse in each direction. When configured for 8.192 Mbps H-MVIP operation, the FREEDM-32A672 partitions the 32 physical links into 8 logical groups of 4 links. All links configured for 8.192 Mbps H-MVIP operation will share a common type 0 frame pulse, a common frame pulse clock and a common data clock. For channelised T1/J1/E1 links, the FREEDM-32A672 allows up to 672 bidirectional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed T1/J1/E1 links. For unchannelised links, the FREEDM-32A672 processes up to 32 bi-directional HDLC channels within 32 independently timed links. Each data stream can be HDLC processed on a channelised basis within the Receive HDLC Processor / Partial Packet Buffer (RHDL672) and Transmit HDLC Processor / Partial Packet Buffer (THDL672). There is a 32 Kbyte buffer in the
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S YS C LK
R S TB
Figure 1 - FREEDM-32A672 Block Diagram
R D [31 :0] R C LK [31:0] R FP B [3:0] R M V C K [3 :0 ] R M V 8D C R M V 8FP C R FP 8 B R eceive H DLC P rocesso r/ P artial P a cke t B uffe r (R H DL6 72) P erform an ce M o nitor (P M O N )
P M C TE S T
R eceive C han nel A ssign er (R C A S 672)
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TD [3 1:0 ] TC LK [3 1:0] TFP B [3:0] TM V C K [3:0] TM V 8D C TM V 8F P C TF P 8 B Tran sm it H D L C P ro ce ssor/ P artial P a cke t B uffe r (TH D L67 2) Tra nsm it A ny-P H Y P acket Inte rfa ce (TA P I6 72 )
Tra nsm it C han nel A ssign er (TC A S 67 2)
R B C LK
RBD
ISSUE 1
R eceive A ny-P H Y P acket Inte rfa ce (R A P I67 2)
R XC L K R XA D D R [2:0 ] RPA RENB R XD A TA [1 5:0] R X P R TY RSX REOP RMOD R E RR
M icro pro cessor Inte rfa ce JTA G P ort
TX C L K TXA D D R [1 2:0] TP A 1[2 :0 ] TP A 2[2 :0 ] TR D Y TXD A TA [15 :0 ] TX P R TY TS X TE O P TM O D TE R R
RHDL672 and another 32 Kbyte buffer in the THDL672 that must be assigned to FREEDM-32A672 channels to serve as channel FIFO's. Each buffer is a group of 2048 blocks with 16 bytes per block, and a minimum of 3 blocks must be assigned to a channel during provisioning. This allows for flexible assignment of a channel FIFO based on the expected data rate for the channel.
5
IN TB RDB W RB CSB A LE A [11:2 ] D [1 5:0 ]
PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
TB C LK
TB D
TD O TD I TC K TM S TR S TB
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Alternatively, the RHDL672 and THDL672 can provision a channel as transparent, in which case, the raw data stream is transferred without HDLC processing. The Receive Any-PHY Interface (RAPI672) provides a low latency path for transferring data out of the partial packet buffer in the RHDL672 and onto the Receive Any-PHY Packet Interface (Rx APPI). The RAPI672 contains a FIFO block for latency control as well as to segregate the APPI timing domain from the SYSCLK timing domain. The RAPI672 contains the necessary logic to manage and respond to device polling from an upper layer device. The RAPI672 also provides the upper layer device with status information on a per packet basis. The Transmit Any-PHY Interface (TAPI672) provides a low latency path for transferring data from the Transmit Any-PHY Packet Interface (Tx APPI) into the partial packet buffer in the THDL672. The TAPI672 contains a FIFO block for latency control as well as to segregate the APPI timing domain from the SYSCLK timing domain. The TAPI672 contains the necessary logic to manage and respond to channel polling from an upper layer device. The PMON block provides performance monitor counts for a number of events. These counters can be read via the microprocessor interface and provides a means for the host software to accumulate performance statistics. Channelised T1/J1/E1 and unchannelised links can be individually placed in line loopback. In addition to the line loopback capability, the FREEDM-32A672 provides a BERT port for attachment to BERT hardware. Under software control this port can be connected to any one of the 32 bi-directional links for additional diagnostic testing. The line loopback and BERT features are not supported for H-MVIP links. Finally, there is an internal diagnostic loopback configuration for each channel which can be used to diagnose FREEDM-32A672 operation on a per channel basis. 3.2 Any-PHY Packet Interface The FREEDM-32A672 provides a low latency "Any-PHY" Packet Interface (APPI) to allow an external controller direct access into the 32 Kbyte partial packet buffers. Up to seven FREEDM-32A672 devices may share a single APPI. For each of the transmit and receive APPI, the external controller is the master of each FREEDM-32A672 device sharing the APPI from the point of view of device selection. The external controller is also the master for channel selection in the transmit direction. In the receive direction, however, each FREEDM-32A672 device retains control over selection of its respective channels. The transmit and receive APPI is made up of three groups of functional signals - polling, selection
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and data transfer. The polling signals are used by the external controller to interrogate the status of the transmit and receive 32 Kbyte partial packet buffers. The selection signals are used by the external controller to select a FREEDM32A672 device, or a channel within a FREEDM-32A672 device, for data transfer. The data transfer signals provide a means of transferring data across the APPI between the external controller and a FREEDM-32A672 device. In the receive direction, polling and selection are done at the device level. Polling is not decoupled from selection, as the receive address pins serve as both a device poll address and to select a FREEDM-32A672 device. In response to a positive poll, the external controller may select that FREEDM-32A672 device for data transfer. Once selected, the FREEDM-32A672 prepends an in-band channel address to each partial packet transfer across the receive APPI to associate the data with a channel. A FREEDM-32A672 must not be selected after a negative poll response. In the transmit direction, polling is done at the channel level. Polling is completely decoupled from selection. To increase the polling bandwidth, up to two channels may be polled simultaneously. The polling engine in the external controller runs independently of other activity on the transmit APPI. In response to a positive poll, the external controller may commence partial packet data transfer across the transmit APPI for the successfully polled channel of a FREEDM-32A672 device. The external controller must prepend an in-band channel address to each partial packet transfer across the transmit APPI to associate the data with a channel. Detailed information on configuring the RAPI672 and the TAPI672 can be found in section 6 of this document.
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4
INTERRUPT ARCHITECTURE This section provides an overview of the FREEDM-32A672 interrupt architecture. Detailed information on the individual interrupts is available in the Longform Datasheet[1]. The FREEDM-32A672 provides a number of individual interrupts which are identified as 'I' bits within the FREEDM-32A672 Master Interrupt Status (0x008) register. When an interrupt source becomes active, the 'I' bit is set and remains set until the FREEDM-32A672 Master Interrupt Status (0x008) register is read. The FREEDM-32A672 provides interrupts to the microprocessor via the INTB pin of the FREEDM-32A672. The INTB pin is gated by the FREEDM-32A672 Master Interrupt Enable (0x004) register. This register contains 'E' bits which can mask the 'I' bit from causing an interrupt on the INTB pin of the FREEDM32A672. When the 'E' and 'I' bits of an interrupt source are both high, then the INTB pin is active. When the 'E' bit is low, the interrupt source will not activate the INTB pin, regardless of the 'I' bit status. However, the `I' bit remains valid when interrupts are disabled and may be polled to detect the various events. The complete list of 'I' bits and 'E' bits is shown below: `E' Bit RFCSEE RABRTE RPFEE RFOVRE TPRTYE TUNPVE TFOVRE TFUDRE `I' Bit RFCSEI RABRTI RPFEI RFOVRI TPRTYI TUNPVI TFOVRI TFUDRI Description Receive FCS Error Receive Abort Receive Packet Format Error Receive FIFO Overrun Error Transmit Parity Error Transmit Unprovisioned Error Transmit FIFO Overflow Error Transmit FIFO Underflow Error
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5
CONFIGURING THE SERIAL LINKS Each of the 32-bidirectional links is controlled via the RCAS672 and the TCAS672 blocks of the FREEDM-32A672. The RCAS672 controls the receive data stream while the TCAS672 controls the transmit data stream. The RCAS672 extracts data bits from each of 32 receive links, based on the link configuration specified in the Normal Mode Register Space. The RCAS672 can align data to a link's gapped clock in channelised mode, extract unaligned data in unchannelised mode, or extract byte synchronized data in unchannelised mode. The TCAS672 sources data bits onto each of 32 transmit links, based on the link configuration specified in the Normal Mode Register Space. The TCAS672 can provide data aligned to a link's gapped clock in channelised mode, provide unaligned data in unchannelised mode, or provide byte synchronized data in unchannelised mode. Each of the serial link configurations is discussed separately in the following sections.
5.1
Channelised T1/J1 Links The receive bit stream is input on RD[n], and the RCLK[n] input is a 1.544 MHz clock that provides bit timing. The clock is gapped to align time-slot 1 of the channelised T1/J1 receive link (see Figure 2). The transmit bit stream is output on TD[n], and the TCLK[n] input is a 1.544 MHz clock that provides bit timing. The clock is gapped to align time-slot 1 of the channelised T1/J1 transmit link (see Figure 3). In each direction, transmit or receive, a T1/J1 frame consists of 24 time-slots or bytes which are mapped to one or more channels of the FREEDM-32A672. The data stream of each direction is processed and clocked independently. Figure 2 - Channelised T1/J1 Receive Link Timing RCLK[n] RD[n]
B7 B8 F B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 TS 24 TS 1 TS 2
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Figure 3 - Channelised T1/J1 Transmit Link Timing TCLK[n] TD[n]
B7 B8 TS 24 B1 F B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 TS 1 TS 2
To configure the RCAS672 and TCAS672 to interface to channelised T1/J1 links, the following bits are written: Bit MODE[2:0] BSYNC FTHRES[6:0] MODE[2:0] BSYNC FTHRES[6:0] FDATA[7:0] Notes: * The RCAS Link #n Configuration register must be chosen from the range 0x180 through 0x1FC corresponding to the link being configured for channelised T1/J1 operation. The BSYNC bit is present only in registers with 0 n 2. The BSYNC value is ignored for the channelised mode of operation. The TCAS Link #n Configuration register must be chosen from the range 0x480 through 0x4FC corresponding to the link being configured for channelised T1/J1 operation. The BSYNC bit is present only in registers with 0 n 2. The BSYNC value is ignored for the channelised mode of operation. The FTHRES[6:0] value assumes a SYSCLK of 40Mhz. For other values of SYSCLK the framing threshold value is 1.5 fSYSCLK / 1.544 MHz. (This value ensures that the threshold is suitable for T1/J1 and E1 links). The FDATA[7:0] bits of the TCAS Idle Time-slot Fill Data (0x40C) register, and the FTHRES[6:0] bits of the RCAS Framing Bit Threshold (0x108) / TCAS Framing Bit Threshold (0x408) registers, affect all links of a Register RCAS Link #n Configuration (0x180 - 0x1FC) RCAS Link #n Configuration (0x180 - 0x188) RCAS Framing Bit Threshold (0x108) TCAS Link #n Configuration (0x480 - 0x4FC) TCAS Link #n Configuration (0x480 - 0x488) TCAS Framing Bit Threshold (0x408) TCAS Idle Time-slot Fill Data (0x40C) Value 001 X 0x25 001 X 0x25 0xFF
*
*
*
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FREEDM-32A672. The programmer should ensure that these values are suitable for all links attached to a FREEDM-32A672. 5.2 Channelised E1 Links The receive bit stream is input on RD[n], and the RCLK[n] input is a 2.048 MHz clock that provides bit timing. The clock is gapped to align time-slot 1 of the channelised E1 receive link (see Figure 4). The transmit bit stream is output on TD[n], and the TCLK[n] input is a 2.048 MHz clock that provides bit timing. The clock is gapped to align time-slot 1 of the channelised E1 transmit link (see Figure 5). In each direction, transmit or receive, an E1 frame consists of 31 time-slots or bytes which are mapped to one or more channels of the FREEDM-32A672. The data stream of each direction is processed and clocked independently. Figure 4 - Channelised E1 Receive Link Timing RCLK[n] RD[n]
B6 B7 B8 F1 F2 F3 F4 F5 F6 F7 F8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 TS 31 FAS / NFAS TS 1 TS 2
Figure 5 - Channelised E1 Transmit Link Timing TCLK[n] TD[n]
B6 B7 B8 TS 31 B1 FAS / NFAS B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 TS 1 TS 2
To configure the RCAS672 and TCAS672 to interface to channelised E1 links, the following bits are written: Bit MODE[2:0] BSYNC FTHRES[6:0] Register RCAS Link #n Configuration (0x180 - 0x1FC) RCAS Link #n Configuration (0x180 - 0x188) RCAS Framing Bit Threshold (0x108) Value 010 X 0x25
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Bit MODE[2:0] BSYNC FTHRES[6:0] FDATA[7:0] Notes: *
Register TCAS Link #n Configuration (0x480 - 0x4FC) TCAS Link #n Configuration (0x480 - 0x488) TCAS Framing Bit Threshold (0x408) TCAS Idle Time-slot Fill Data (0x40C)
Value 010 X 0x25 0xFF
The RCAS Link #n Configuration register must be chosen from the range 0x180 through 0x1FC corresponding to the link being configured for channelised E1 operation. The BSYNC bit is present only in registers with 0 n 2. The BSYNC value is ignored for the channelised mode of operation. The TCAS Link #n Configuration register must be chosen from the range 0x480 through 0x4FC corresponding to the link being configured for channelised E1 operation. The BSYNC bit is present only in registers with 0 n 2. The BSYNC value is ignored for the channelised mode of operation. Since channelised E1 links have a framing byte, its gap will always be longer than the gap for the T1/J1 framing bit. Therefore, the same FTHRES[6:0] value of 0x25 can be used. The FTHRES[6:0] value assumes a SYSCLK of 40Mhz. For other values of SYSCLK the framing threshold value is 1.5 fSYSCLK / 1.544 MHz. (This value ensures the threshold is suitable for T1/J1 and E1 links). The FDATA[7:0] bits of the TCAS Idle Time-slot Fill Data (0x40C) register, and the FTHRES[6:0] bits of the RCAS Framing Bit Threshold (0x108) / TCAS Framing Bit Threshold (0x408) registers, affect all links of a FREEDM-32A672. The programmer should ensure that these values are suitable for all links attached to a FREEDM-32A672.
*
*
*
5.3
Unchannelised Links with Byte Synchronization The bit stream of the unchannelised receive link that is attached to the RD[n] input is sampled on rising edges of the RCLK[n] input (see Figure 6). The receive data is byte aligned to the gapped RCLK[n] input, with the most significant bit of the byte clocked in following the gap. The unchannelised transmit link is attached to the TD[n] output and is driven on falling edges of the TCLK[n] input (see Figure 7). The transmit data is byte
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aligned to the gapped TCLK[n] input, with the most significant bit of the byte clocked out during the gap. This mode of operation is only available for links 0 through 2 of a FREEDM32A672. In each direction, transmit or receive, the data stream is processed and clocked independently. Figure 6 - Unchannelised Receive Link Timing with Byte Synchronization
RCLK[n] RD[n]
*# *$ *% *& * * *! *" *# *$ *% *& * * *! *"
Figure 7 - Unchannelised Transmit Link Timing with Byte Synchronization
TCLK[n] TD[n]
B5 B6 B7 B8 B1 B1 B1 B1 B1 B1 B1 B1 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4
To configure the RCAS672 and TCAS672 to interface to byte synchronized unchannelised links, the following bits are written: Bit MODE[2:0] BSYNC FTHRES[6:0] MODE[2:0] BSYNC FTHRES[6:0] FDATA[7:0] Notes: * The RCAS Link #n Configuration register must be chosen from the range 0x180 through 0x1FC corresponding to the link being configured. The Register RCAS Link #n Configuration (0x180 - 0x1FC) RCAS Link #n Configuration (0x180 - 0x188) RCAS Framing Bit Threshold (0x108) TCAS Link #n Configuration (0x480 - 0x4FC) TCAS Link #n Configuration (0x480 - 0x488) TCAS Framing Bit Threshold (0x408) TCAS Idle Time-slot Fill Data (0x40C) Value 000 1 see note 000 1 see note 0xFF
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
unchannelised link with byte synchronization is only supported in registers with 0 n 2. * The TCAS Link #n Configuration register must be chosen from the range 0x480 through 0x4FC corresponding to the link being configured. The unchannelised link with byte synchronization is only supported in registers with 0 n 2. The FTHRES[6:0] must be set based on the expected gap width of RCLK[n] or TCLK[n]. The reader should refer to the Longform Datasheet[1] on how to set this value. The FDATA[7:0] bits of the TCAS Idle Time-slot Fill Data (0x40C) register, and the FTHRES[6:0] bits of the RCAS Framing Bit Threshold (0x108) / TCAS Framing Bit Threshold (0x408) registers, affect all links of a FREEDM-32A672. The programmer should ensure that these values are suitable for all links attached to a FREEDM-32A672.
*
*
5.4
Unchannelised Links without Synchronization The bit stream of the unchannelised receive link that is attached to the RD[n] input is sampled on rising edges of the RCLK[n] input (see Figure 8). The receive data is not aligned to the RCLK[n] input. The unchannelised transmit link is attached to the TD[n] output and is driven on falling edges of the TCLK[n] input (see Figure 9). The transmit data is not aligned to the TCLK[n] input. In each direction, transmit or receive, the data stream is processed and clocked independently. Figure 8 - Unchannelised Receive Link Timing without Synchronization
RCLK[n] RD[n]
B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
Figure 9 - Unchannelised Transmit Link Timing without Synchronization TCLK[n] TD[n]
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2
To configure the RCAS672 and TCAS672 to interface to unchannelised links without synchronization, the following bits are written: Bit MODE[2:0] BSYNC FTHRES[6:0] MODE[2:0] BSYNC FTHRES[6:0] FDATA[7:0] Notes: * The RCAS Link #n Configuration register must be chosen from the range 0x180 through 0x1FC corresponding to the link being configured for unchannelised operation. The TCAS Link #n Configuration register must be chosen from the range 0x480 through 0x4FC corresponding to the link being configured for unchannelised operation. The BSYNC bit must only be programmed for links where 0 n 2. For other links, there is no BSYNC bit. The FTHRES[6:0] bits of the RCAS Framing Bit Threshold (0x108) / TCAS Framing Bit Threshold (0x408) registers have no effect on the operation of an unchannelised link with BSYNC low, or on unchannelised links with no BSYNC bit. The FDATA[7:0] bits of the TCAS Idle Time-slot Fill Data (0x40C) register, and the FTHRES[6:0] bits of the RCAS Framing Bit Threshold (0x108) / TCAS Framing Bit Threshold (0x408) registers, affect all links of a Register RCAS Link #n Configuration (0x180 - 0x1FC) RCAS Link #n Configuration (0x180 - 0x188) RCAS Framing Bit Threshold (0x108) TCAS Link #n Configuration (0x480 - 0x4FC) TCAS Link #n Configuration (0x480 - 0x488) TCAS Framing Bit Threshold (0x408) TCAS Idle Time-slot Fill Data (0x40C) Value 000 0 XXH 000 0 XXH 0xFF
*
* *
*
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
FREEDM-32A672. The programmer should ensure that these values are suitable for all links attached to a FREEDM-32A672. 5.5 8.192 Mbps H-MVIP Links The timing relationship of the receive data clock (RMV8DC), frame pulse clock (RMV8FPC), data (RD[n]) and frame pulse (RFP8B[n]) signals of a link configured for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 10. The falling edges of each RMV8FPC are aligned to a falling edge of the corresponding RMV8DC for 8.192 Mbps H-MVIP operation. The FREEDM32A672 samples RFP8B low on the falling edge of RMV8FPC and references this point as the start of the next frame. The FREEDM-32A672 samples the data provided on RD[n] at the 3/4 point of the data bit using the rising edge of RMV8DC as indicated for bit 1 (B1) of time-slot 0 (TS 0) in Figure 10. B1 is the most significant bit and B8 is the least significant bit of each octet. Time-slots can be ignored by setting the PROV bit in the corresponding word of the receive channel provision RAM in the RCAS672 block to low. Figure 10 - Receive 8.192 Mbps H-MVIP Link Timing
RM V8DC (16 M H z)
R M V 8F P C (4 M H z)
R F P 8B
R D [n ]
B8 T S 127
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
The timing relationship of the transmit data clock (TMV8DC), frame pulse clock (TMV8FPC), data (TD[n]) and frame pulse (TFP8B) signals of a link configured for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 11. The falling edges of each TMV8FPC are aligned to a falling edge of the corresponding TMV8DC for 8.192 Mbps H-MVIP operation. The FREEDM32A672 samples TFP8B low on the falling edge of TMV8FPC and references this point as the start of the next frame. The FREEDM-32A672 updates the data provided on TD[n] on every second falling edge of TMV8DC as indicated for bit 2 (B2) of time-slot 0 (TS 0) in Figure 11. The first bit of the next frame is updated on TD[n] on the falling TMV8DC clock edge for which TFP8B is also sampled low. B1 is the most significant bit and B8 is the least significant bit of each octet.
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
Time-slots that are not provisioned to belong to any channel (PROV bit in the corresponding word of the transmit channel provision RAM in the TCAS672 block set low) transmits the contents of the TCAS Idle Time-slot Fill Data (0x40C) register. Figure 11 - Transmit 8.192 Mbps H-MVIP Link Timing
TM V8DC (16 M H z)
TM V8FPC (4 M H z)
T F P 8B
T D [n]
B8 T S 127
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
To configure the RCAS672 and TCAS672 to interface to 8.192 Mbps H-MVIP links, the following bits are written: Bit MODE[2:0] BSYNC FTHRES[6:0] MODE[2:0] BSYNC FTHRES[6:0] FDATA[7:0] Notes: * When link 4m (0m7) is configured for operation in 8.192 Mbps H-MVIP mode (MODE[2:0]="111"), data cannot be received on links 4m+1, 4m+2 and 4m+3. However, links 4m+1, 4m+2 and 4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation of the RCAS672. From a channel assignment point of view in the RCAS672 (Registers 0x100, 0x104), timeslots 0 through 31 of the H-MVIP link are treated as time-slots 0 through 31 of Register RCAS Link #n Configuration (0x180 - 0x1FC) RCAS Link #n Configuration (0x180 - 0x188) RCAS Framing Bit Threshold (0x108) TCAS Link #n Configuration (0x480 - 0x4FC) TCAS Link #n Configuration (0x480 - 0x488) TCAS Framing Bit Threshold (0x408) TCAS Idle Time-slot Fill Data (0x40C) Value 111 X XXH 111 X XXH 0xFF
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
link 4m, time-slots 32 through 63 of the H-MVIP link are treated as time-slots 0 through 31 of link 4m+1, time-slots 64 through 95 of the H-MVIP link are treated as time-slots 0 through 31 of link 4m+2 and time-slots 96 through 127 of the H-MVIP link are treated as time-slots 0 through 31 of link 4m+3. * When link 4m (0m7) is configured for operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 are driven with constant ones. However, links 4m+1, 4m+2 and 4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation of the TCAS672. From a channel assignment point of view in the TCAS672 (Registers 0x40, 0x404), time-slots 0 through 31 of link 4m are mapped to time-slots 0 through 31 of the H-MVIP link, timeslots 0 through 31 of link 4m+1 are mapped to time-slots 32 through 63 of the H-MVIP link, time-slots 0 through 31 of link 4m+2 are mapped to time-slots 64 through 95 of the H-MVIP link and time-slots 0 through 31 of link 4m+3 are mapped to time-slots 96 through 127 of the H-MVIP link. The BSYNC value is ignored for links configured for H-MVIP . The FTHRES[6:0] bits of the RCAS Framing Bit Threshold (0x108) / TCAS Framing Bit Threshold (0x408) registers have no effect on the operation of H-MVIP links. The FDATA[7:0] bits of the TCAS Idle Time-slot Fill Data (0x40C) register, and the FTHRES[6:0] bits of the RCAS Framing Bit Threshold (0x108) / TCAS Framing Bit Threshold (0x408) registers, affect all links of a FREEDM-32A672. The programmer should ensure that these values are suitable for all links attached to a FREEDM-32A672.
* *
*
5.6
2.048 Mbps H-MVIP Links The timing relationship of the receive data clock (RMVCK[n]), data (RD[m], where 8nm8n+7) and frame pulse (RFPB[n]) signals of a link configured for 2.048 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 12. The FREEDM-32A672 samples RFPB[n] low on the falling edge of the corresponding RMVCK[n] and references this point as the start of the next frame. The FREEDM-32A672 samples the data provided on RD[m] at the 3/4 point of the data bit using the rising edge of the corresponding RMVCK[n] as indicated for bit 1 (B1) of time-slot 0 (TS 0) in Figure 12. B1 is the most significant bit and B8 is the least significant bit of each octet. Time-slots can be ignored by setting the PROV bit in the corresponding word of the receive channel provision RAM in the RCAS672 block to low.
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
Figure 12 - Receive 2.048 Mbps H-MVIP Link Timing
R M V C K [n] (4 M H z)
R F P B [n]
R D [m ]
B8 T S 31
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
The timing relationship of the transmit data clock (TMVCK[n]), data (TD[m], where 8nm8n+7) and frame pulse (TFPB[n]) signals of a link configured for 2.048 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 13. The FREEDM-32A672 samples TFPB[n] low on the falling edge of the corresponding TMVCK[n] and references this point as the start of the next frame. The FREEDM-32A672 updates the data provided on TD[m] on every second falling edge of the corresponding TMVCK[n] as indicated for bit 2 (B2) of time-slot 0 (TS 0) in Figure 13. The first bit of the next frame is updated on TD[n] on the falling TMVCK[n] clock edge for which TFPB[n] is also sampled low. B1 is the most significant bit and B8 is the least significant bit of each octet. Time-slots that are not provisioned to belong to any channel (PROV bit in the corresponding word of the transmit channel provision RAM in the TCAS672 block set low) transmits the contents of the TCAS Idle Time-slot Fill Data (0x40C) register. Figure 13 - Transmit 2.048 Mbps H-MVIP Link Timing
T M V C K [n] (4 M H z)
T FP B [n]
T D [m ]
B8 T S 31
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
To configure the RCAS672 and TCAS672 to interface to 2.048 Mbps H-MVIP links, the following bits are written: Bit MODE[2:0] Register RCAS Link #n Configuration (0x180 - 0x1FC) Value 011
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
Bit BSYNC FTHRES[6:0] MODE[2:0] BSYNC FTHRES[6:0] FDATA[7:0] Notes: *
Register RCAS Link #n Configuration (0x180 - 0x188) RCAS Framing Bit Threshold (0x108) TCAS Link #n Configuration (0x480 - 0x4FC) TCAS Link #n Configuration (0x480 - 0x488) TCAS Framing Bit Threshold (0x408) TCAS Idle Time-slot Fill Data (0x40C)
Value X XXH 011 X XXH 0xFF
The RCAS Link #n Configuration register must be chosen from the range 0x180 through 0x1FC corresponding to the link being configured for 2.048 Mbps H-MVIP operation. The TCAS Link #n Configuration register must be chosen from the range 0x480 through 0x4FC corresponding to the link being configured for 2.048 Mbps H-MVIP operation. The BSYNC value is ignored for links configured for H-MVIP . The FTHRES[6:0] bits of the RCAS Framing Bit Threshold (0x108) / TCAS Framing Bit Threshold (0x408) registers have no effect on the operation of H-MVIP links. The FDATA[7:0] bits of the TCAS Idle Time-slot Fill Data (0x40C) register, and the FTHRES[6:0] bits of the RCAS Framing Bit Threshold (0x108) / TCAS Framing Bit Threshold (0x408) registers, affect all links of a FREEDM-32A672. The programmer should ensure that these values are suitable for all links attached to a FREEDM-32A672.
*
* *
*
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
6
CONFIGURING THE ANY-PHY PACKET INTERFACE The RAPI672 and TAPI672 blocks must be configured via the normal mode registers in order to enable the transferring of data between the partial packet buffers and the receive and transmit APPI.
6.1
Configuring the Receive Any-PHY Packet Interface (RAPI672) The RAPI672 is configured by programming bits within the RAPI Control (0x580) register. The values programmed affect all receive channels. The default configuration is as follows: Bit BADDR[2:0] ALL1ENB Reserved STATEN ENABLE Register RAPI Control (0x580) RAPI Control (0x580) RAPI Control (0x580) RAPI Control (0x580) RAPI Control (0x580) Value 111 1 0 0 0
The default indicates that the RAPI672 is disabled from responding to device selection. Activation of the RAPI672 By default, the RAPI672 is disabled from responding to device selection. The ENABLE bit must be set to enable normal operation of the RAPI672. The encoding of this bit is: ENABLE 0 1 Function The RAPI672 will not respond to device selection. The RAPI672 operates normally, and will respond to device selection.
Base Address of the Receive APPI The base address bits (BADDR[2:0]) configure the address space occupied by the FREEDM-32A672 device for purposes of responding to receive polling and receive device selection. During polling, the BADDR[2:0] bits are used to respond to polling via the RXADDR[2:0] pins. During device selection, the
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
BADDR[2:0] are used to select a FREEDM-32A672 device, enabling it to accept data on the receive APPI. During data transfer, the RXDATA[15:13] pins of the prepended channel address reflect the BADDR[2:0] bits. All Ones Enable The All Ones Enable bit (ALL1ENB) permits the FREEDM-32A672 to respond to receive polling and device selection when BADDR[2:0] = `111'. The encoding of this bit is: ALL1ENB 0 1 Function The FREEDM-32A672 responds to receive polling and device selection when BADDR[2:0] = RXADDR[2:0] = `111'. The FREEDM-32A672 regards the all-ones address as a null address and does not respond to receive polling and device selection when BADDR[2:0] = `111', regardless of the value of RXADDR[2:0].
Status Enable The FREEDM-32A672 can be programmed to overwrite the receive data signal pins, RXDATA[7:0], of the final word of each packet transfer (REOP pin is high) with the status of packet reception when that packet is errored (RERR pin is high). The RAPI672 Status Enable bit enables this feature as follows: STATEN 0 1 Function The RAPI672 does not report detailed status information for an errored packet. The RAPI672 overwrites RXDATA[7:0] of the final word of an errored packet with status information for that packet.
When STATEN = 1 and the REOP and RERR pins are both high, the status information is bit mapped on RXDATA[7:0] as follows: Bit RXDATA[0] = 1 RXDATA[1] = 1 RXDATA[2] = 1 RXDATA[3] = 1 Channel FIFO overrun Maximum packet length violation FCS error Non-octet aligned Status
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PM7381 FREEDM-32A672
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Bit RXDATA[4] = 1 RXDATA[7:5] = XH 6.2 HDLC packet abort Reserved
Status
Configuring the Transmit Any-PHY Packet Interface (TAPI672) The TAPI672 is configured by programming bits within the TAPI Control (0x600) register. The values programmed affect all transmit channels. The default configuration is as follows: Bit BADDR[2:0] ALL1ENB Reserved[1:0] ENABLE BLEN[7:0] Register TAPI Control (0x600) TAPI Control (0x600) TAPI Control (0x600) TAPI Control (0x600) TAPI Indirect Channel Data Register (0x608) Value 111 1 00 0 0x00
The default indicates that data provided to the TAPI672 by the transmit APPI will be ignored. Activation of the TAPI672 By default, data provided to the TAPI672 by the transmit APPI is ignored. The ENABLE bit must be set to enable normal operation of the TAPI672. The encoding of this bit is: ENABLE 0 Function The state machines in the TAPI672 are held in their idle state. The TAPI672 will complete the current data transfer and will respond to any further transactions on the transmit APPI normally (by setting TRDY high), but data provided will be ignored. The TAPI672 operates normally. Data can be transferred from the transmit APPI to the partial packet buffer in the THDL672.
1
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PM7381 FREEDM-32A672
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Base Address of the Receive APPI The base address bits (BADDR[2:0]) configure the address space occupied by the FREEDM-32A672 device for purposes of responding to transmit polling and transmit data transfers. During polling, the TXADDR[12:10] pins are compared with the BADDR[2:0] bits to determine if the poll address identified by TXADDR[9:0] is intended for a channel in this FREEDM-32A672 device. During data transmission, the TXDATA[15:13] pins of the prepended channel address are compared with the BADDR[2:0] bits to determine if the data to follow is intended for this FREEDM-32A672 device. All Ones Enable The All Ones Enable bit (ALL1ENB) permits the FREEDM-32A672 to respond to transmit polling and device selection when BADDR[2:0] = `111'. The encoding of this bit is: ALL1ENB 0 Function The FREEDM-32A672 responds to transmit polling when BADDR[2:0] = TXADDR[12:10] = `111' and device selection when BADDR[2:0] = TXDATA[15:13] = `111'. The FREEDM-32A672 regards the all-ones address as a null address and does not respond to transmit polling and device selection when BADDR[2:0] = `111', regardless of the values of TXADDR[12:10] and TXDATA[15:13].
1
Channel Burst Length The channel burst length (BLEN[7:0]) bits report the data transfer burst length read from the TAPI672 channel provision RAM after an indirect read operation has completed. The data transfer burst length specifies the length (in bytes, less one) of burst data transfers on the transmit APPI which are not terminated by the assertion of TEOP The data transfer burst length can be specified on a per. channel basis with burst lengths of up to 256 bytes. The data transfer burst length to be written to the channel provision RAM in an indirect write operation must be set up in this register before triggering the write. BLEN[7:0] reflects the value written until the completion of a subsequent indirect read operation. The BLEN[7:0] value must be set according to the indirect channel transfer size of the THDL672 block (XFER[3:0] in the THDL Indirect Channel Data #3 (0x38C) register) using the following equation:
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PM7381 FREEDM-32A672
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BLEN[7:0] = (XFER[3:0] + 1)x16 -1. A description of the XFER[3:0] bits can be found in section 7.5. The relationship between XFER[3:0] and BLEN[7:0] is shown in the following table.
XFER[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
BLEN[7:0] 0x0F 0x1F 0x2F 0x3F 0x4F 0x5F 0x6F 0x7F 0x8F 0x9F 0xAF 0xBF 0xCF 0xDF 0xEF 0xFF
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PM7381 FREEDM-32A672
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7
HDLC AND CHANNEL FIFO CONFIGURATION The FREEDM-32A672 processes the data stream in the receive direction via the RHDL672 block and it processes the data stream in the transmit direction via the THDL672 block. Each of these blocks must be configured via the normal mode registers.
7.1
Configuring the RHDL672 The RHDL672 is configured by programming bits within the RHDL Configuration (0x220) register and the RHDL Maximum Packet Length (0x224) register. The values programmed affect all receive channels. The default configuration is as follows: Bit LENCHK TSTD MAX[15:0] Register RHDL Configuration (0x220) RHDL Configuration (0x220) RHDL Maximum Packet Length (0x224) Value 0 0 0xFFFF
The default indicates no maximum packet length checking and datacom bit ordering. Maximum Packet Length The RHDL672 may be configured to abort packets which exceed the maximum length of n where 0 n 0xFFFF. The following bits are written to enable or disable this feature: LENCHK 0 1 MAX[15:0] 0xFFFF n Function Receive packets are not checked for maximum size and MAX[15:0] must be set to 0xFFFF. Receive packets with total length, including address, control, information and FCS fields, greater than MAX[15:0] bytes are aborted and the remainder of the frame discarded.
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PM7381 FREEDM-32A672
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Datacom/Telecom Bit Order The RHDL672 may be configured to reverse the order of bits in the HDLC data transferred across the receive APPI. The following bit is written to specify the order of bits: TSTD 0 Function Datacom standard: least significant bit of each byte on the receive APPI bus (AD[0] and AD[8]) is the first HDLC bit received. Normally, when HDLC processing is enabled, the TSTD bit must be set to zero. Telecom standard: most significant bit of each byte on the receive APPI bus (AD[7] and AD[15]) is the first HDLC bit received.
1
7.2
Configuring the THDL672 The THDL672 is configured by programming bits within the THDL Configuration (0x3B0) register. The values programmed affect all transmit channels. The default configuration is as follows: Bit Reserved[3:0] Reserved[4] TSTD BIT8 Register THDL Configuration (0x3B0) THDL Configuration (0x3B0) THDL Configuration (0x3B0) THDL Configuration (0x3B0) Value 0x0 0 0 0
The default indicates that data is formatted in datacom bit ordering. Datacom/Telecom Bit Order The THDL672 may be configured to reverse the order of bits in the HDLC data transferred on the transmit APPI. The following bit is written to specify the order of bits: TSTD 0 Function Datacom standard: least significant bit of each byte on the transmit APPI bus (AD[0] and AD[8]) is the first HDLC bit transmitted. Normally, when HDLC processing is enabled, the TSTD bit must be set to zero.
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PM7381 FREEDM-32A672
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TSTD 1
Function Telecom standard: most significant bit of each byte on the transmit APPI bus (AD[7] and AD[15]) is the first HDLC bit transmitted.
BIT8 The BIT8 field affects channels of the THDL672 that are configured with 7BIT set. The BIT8 value specifies the data bit transmitted on the least significant bit of each octet. BIT8 0 1 Function Channels configured for 7BIT will transmit a zero on the least significant bit of each octet. Channels configured for 7BIT will transmit a one on the least significant bit of each octet.
7.3
Programming a Channel FIFO A Channel FIFO is created from 3 or more blocks of internal RAM, and each block holds 16 bytes of packet data. There is a total of 2048 blocks (32 Kbytes) available to assign among the receive channels, and another 2048 blocks (32 Kbytes) available to assign among the transmit channels. A FIFO is created by assigning a circular linked list of blocks as shown in Figure 14. This shows a channel FIFO consisting of 3 blocks. The quantity of buffers and the arrangement of links is chosen by the programmer, and the selection of blocks can be arbitrary. The programmer must ensure that a block is not assigned to more than one circularly linked list.
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PM7381 FREEDM-32A672
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Figure 14 - Specifying a Channel FIFO Partial Packet Buffer RAM
Block 0 Block 1 Block 2 Block 3 16 bytes 16 bytes 16 bytes 16 bytes Block 0 Block 1 Block 2 Block 3
Block Pointer RAM
XXXH BPTR[10:0] = 0x003 XXXH BPTR[10:0] = 0x0C8
Block 200
16 bytes
Block 200
BPTR[10:0] = 0x001
Block 2047
16 bytes
Block 2047
XXXH
7.3.1 Receive Channel FIFO A receive channel FIFO is programmed by repeating the following procedure for each block within the circularly linked list: 1. Poll the BUSY bit of the RHDL Indirect Block Select (0x210) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 2. Write the following register with the next block in the circular linked list, or exit if all links have been programmed: Bit BPTR[10:0] Register RHDL Indirect Block Data (0x214) Value 0 through 0x7FF are valid
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Bit Reserved
Register RHDL Indirect Block Data (0x214)
Value 0
3. Specify the block and update the internal block pointer RAM by writing the following register. Proceed to step 1. Bit BLOCK[10:0] Register RHDL Indirect Block Select (0x210) Value 0 through 0x7FF are valid 0 0 X
Reserved BRWB BUSY
RHDL Indirect Block Select (0x210) RHDL Indirect Block Select (0x210) RHDL Indirect Block Select (0x210)
7.3.2 Transmit Channel FIFO A transmit channel FIFO is programmed by repeating the following procedure for each block within the circularly linked list: 1. Poll the BUSY bit of the THDL Indirect Block Select (0x3A0) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 2. Write the following register with the next block in the circular linked list, or exit if all links have been programmed: Bit BPTR[10:0] Register THDL Indirect Block Data (0x3A4) Value 0 through 0x7FF are valid 0 0
Reserved[0] Reserved[1]
THDL Indirect Block Data (0x3A4) THDL Indirect Block Data (0x3A4)
3. Specify the block and update the internal block pointer RAM by writing the following register. Proceed to step 1.
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Bit BLOCK[10:0]
Register THDL Indirect Block Select (0x3A0)
Value 0 through 0x7FF are valid 0 0 X
Reserved BRWB BUSY 7.4
THDL Indirect Block Select (0x3A0) THDL Indirect Block Select (0x3A0) THDL Indirect Block Select (0x3A0)
RHDL672 Channel Configuration The RHDL672 provides configurable options for each receive channel as identified in the following register fields: Bit DELIN STRIP XFER[3:0] OFFSET[1:0] CRC[1:0] INVERT PRIORITY 7BIT Register RHDL Indirect Channel Data Register #1 (0x204) RHDL Indirect Channel Data Register #1 (0x204) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208)
Note: When writing to RHDL Indirect Channel Data Register #1 (0x204), the reserved bit (bit 11) must be set low for correct operation of the FREEDM32A672. Delineation The data bits from the RCAS672 can be written directly to the Partial Packet Buffer or processed for flag sequence delineation, bit de-stuffing and CRC verification. The following bit enables or disables this feature:
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DELIN 0
Function Data is written to the Partial Packet Buffer without any HDLC processing (no flag sequence delineation, bit de-stuffing nor CRC verification) on the incoming stream. Data is processed for flag sequence delineation, bit destuffing and optionally, CRC verification (CRC verification depends on CRC[1:0] value).
1
Strip FCS Bit The indirect frame check sequence discard bit (STRIP) enables the RHDL672 to remove the FCS data before writing to the channel FIFO. STRIP is ignored when DELIN is low or when CRC[1:0] = 00B. This feature is configured as follows: STRIP 0 1 Function Includes FCS data with the data stream written to the channel FIFO. Removes the FCS data from the data stream written to the channel FIFO.
DMA Transfer Size The indirect channel transfer size configures the amount of data transferred in each transaction. When the channel FIFO depth reaches the depth specified by XFER[3:0] or when an end-of-packet exists in the FIFO, a poll of this FREEDM32A672 device will indicate that data exists and is ready to be transferred across the receive APPI. Specifying a large transfer size may affect APPI bus access latencies for other channels. The following bits specify the channel transfer size: XFER[3:0] 0 through 15 are valid Notes: * XFER[3:0] should be set such that the number of blocks transferred is at least two fewer than the total allocated to the associated channel. Function Specifies the data transfer size in blocks: Blocks = XFER[3:0] +1, and there are 16 bytes per block.
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Insertion of Offset Bytes The RHDL672 can be configured to insert offset bytes into the data stream before writing the data stream to the channel FIFO. The offset bytes are placed before each packet and their value is undefined. The following configuration options are available: OFFSET[1:0] 00 01 10 11 CRC Algorithm The RHDL672 can perform CRC verification of the incoming data stream. The available options are as follows: CRC[1:0] X 00 01 10 11 DELIN 0 1 1 1 1 No CRC verification No CRC verification CRC-CCITT verification CRC-32 verification Reserved Function Function RHDL672 does not insert offset bytes RHDL672 inserts 1 offset byte per packet RHDL672 inserts 2 offset bytes per packet RHDL672 inserts 3 offset bytes per packet
HDLC Data Inversion The INVERT bit configures the RHDL672 to logically invert the incoming HDLC stream from the RCAS672 before processing it. The bit is specified as follows: INVERT 0 1 Function HDLC stream is not inverted. HDLC stream is inverted.
Specifying Receive Channel Priority All receive channels that must transfer data from their channel FIFO to packet memory contend for access to the receive APPI bus. The PRIORITY bit allows
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specified channels to have priority access to the receive APPI bus. The bit encoding is as follows: PRIORITY 0 1 Function This channel is serviced after channels with PRIORITY=1. This channel is serviced before channels with PRIORITY=0.
Handling of Robbed bit Signaling The 7BIT enable configures the RHDL672 to ignore the least significant bit of each octet (last bit of each octet received) in the corresponding link RD[n]. This bit is encoded as follows: 7BIT 0 1 Function The entire receive data stream is processed. The least significant bit (last bit of each octet received) is ignored.
7.5
THDL672 Channel Configuration The THDL672 provides configurable options for each transmit channel as identified in the following register fields: Bit DELIN CRC[1:0] FLEN[10:0] DFCS INVERT 7BIT XFER[3:0] FLAG[2:0] LEVEL[3:0] IDLE TRANS Register THDL Indirect Channel Data Register #1 (0x384) THDL Indirect Channel Data Register #1 (0x384) THDL Indirect Channel Data Register #2 (0x388) THDL Indirect Channel Data Register #2 (0x388) THDL Indirect Channel Data Register #2 (0x388) THDL Indirect Channel Data Register #2 (0x388) THDL Indirect Channel Data Register #3 (0x38C) THDL Indirect Channel Data Register #3 (0x38C) THDL Indirect Channel Data Register #3 (0x38C) THDL Indirect Channel Data Register #3 (0x38C) THDL Indirect Channel Data Register #3 (0x38C)
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Note: When writing to THDL Indirect Channel Data Register #1 (0x384), the reserved bit (bit 11) must be set low for correct operation of the FREEDM32A672. When writing to THDL Indirect Channel Data Register #2 (0x388), the reserved bits (bits 11 and 14) must be set low for correct operation of the FREEDM-32A672. Frame Delineation The transmit packet data from packet memory can be written directly to the outgoing data stream or processed for flag sequence insertion, bit stuffing and CRC generation. The following bit enables or disables this feature: DELIN 0 Function Data is written directly to the outgoing data stream without any HDLC processing (no flag sequence insertion, bit stuffing nor CRC generation). Data is processed for flag sequence insertion, bit stuffing and optionally, CRC generation (CRC generation depends on CRC[1:0] value).
1
CRC Algorithm The THDL672 can perform CRC generation on the outgoing data stream. The available options are as follows: CRC[1:0] X 00 01 10 11 DELIN 0 1 1 1 1 No CRC generation No CRC generation CRC-CCITT generation CRC-32 generation Reserved Function
Channel FIFO Length The indirect FIFO length (FLEN[10:0]) is the number of blocks, less one, that is provisioned to the circular channel FIFO specified by the FPTR[10:0] block pointer.
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FLEN[10:0]
Function
0 through 2047 Specifies the Channel FIFO size in blocks, where Blocks = are valid FLEN[10:0] + 1, and each block is 16 bytes. Inverting the FCS The diagnose frame check sequence bit (DFCS) specifies whether the FCS field inserted into the transmit data stream is inverted. This is provided for diagnostic purposes and is programmed as follows: DFCS 0 1 Function FCS field in the outgoing HDLC stream is not inverted. FCS field in the outgoing HDLC stream is logically inverted.
Robbed Bit Signaling The least significant stuff enable bit (7BIT) configures the THDL672 to stuff the least significant bit of each octet assigned to the transmit channel in the corresponding transmit link (TD[n]). 7BIT 0 1 Function The entire octet contains valid data and BIT8 is ignored. The least significant bit (last bit of each octet transmitted) does not contain channel data and is forced to the value configured by the BIT8 register bit.
DMA Transfer Size The indirect channel transfer size specifies the amount of data that the partial packet processor requests from the TAPI672 block. When the channel FIFO free space reaches or exceeds the limit specified by XFER[3:0], the partial packet processor will inform the TAPI672 so that a poll on that channel reflects that the channel FIFO is able to accept XFER[3:0] + 1 blocks of data. Specifying a large transfer size may affect APPI bus access latencies for other channels. The following bits specify the channel transfer size: XFER[3:0] 0 through 15 are valid Function Specifies the data transfer size in blocks, where Blocks = XFER[3:0] + 1, and each block is 16 bytes.
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Notes: * To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to be less than or equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel transfer size can be set such that the total number of blocks in the logical channel FIFO minus the start transmission level is an integer multiple of the channel transfer size.
Specifying The Number of Flag or Idle Bytes Inserted Between Frames The THDL672 can be configured to insert either flag or idle bytes (8 bits of one's) into the data stream between HDLC packets. The number of these is programmed as follows: FLAG[2:0] 000 001 010 011 100 101 110 111 Interframe Time Fill The IDLE bit specifies the byte pattern inserted in the data stream between HDLC packets. IDLE 0 1 Function Flag bytes are inserted between HDLC packets. HDLC idle (all one's bit with no bit-stuffing) is inserted between HDLC packets. Minimum Number of Flag/Idle Bytes 1 flag / 0 Idle byte 2 flags / 0 idle byte 4 flags / 2 idle bytes 8 flags / 6 idle bytes 16 flags / 14 idle bytes 32 flags / 30 idle bytes 64 flags / 62 idle bytes 128 flags / 126 idle bytes
Specifying the Channel FIFO's Starving Level and Start Transmit Level The HDLC processor starts transmitting a packet when the channel FIFO free space is less than or equal to the level specified in the appropriate Start
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Transmission Level column of the following table or when an end of a packet is stored in the channel FIFO. When the channel FIFO free space is less than or equal to than the level specified in the Starving Trigger Level column of the following table and the HDLC processor is transmitting a packet and an end of a packet is not stored in the channel FIFO, the partial packet buffer makes expedited requests to the TAPI672 to retrieve XFER[3:0] + 1 blocks of data. The starving trigger level and start transmission level are programmed via the LEVEL[3:0] and the TRANS field as follows: LEVEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Starving Trigger Level 2 Blocks (32 bytes free) 3 Blocks (48 bytes free) 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 64 Blocks (1 Kbytes free) 96 Blocks (1.5 Kbytes free) Start Transmission Level (TRANS=0) 1 Block (16 bytes free) 2 Blocks (32 bytes free) 3 Blocks (48 bytes free) 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 64 Blocks (1 Kbytes free) Start Transmission Level (TRANS=1) 1 Block (16 bytes free) 1 Block (16 bytes free) 2 Blocks (32 bytes free) 3 Blocks (48 bytes free) 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free)
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LEVEL[3:0] 1100 1101 1110 1111
Starving Trigger Level 192 Blocks (3 Kbytes free) 384 Blocks (6 Kbytes free) 768 Blocks (12 Kbytes free) 1536 Blocks (24 Kbytes free)
Start Transmission Level (TRANS=0) 128 Blocks (2 Kbytes free) 256 Blocks (4 Kbytes free) 512 Blocks (8 Kbytes free) 1024 Blocks (16 Kbytes free)
Start Transmission Level (TRANS=1) 96 Blocks (1.5 Kbytes free) 192 Blocks (2 Kbytes free) 384 Blocks (4 Kbytes free) 768 Blocks (8 Kbytes free)
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8 8.1
FREEDM-32A672 OPERATIONAL PROCEDURES Device Identification, Location and System Resource Assignment This section describes the software interaction required to identify a FREEDM32A672 device on the APPI bus, and to map the Normal Mode Registers in the microprocessor memory map. Identifying and Locating a FREEDM-32A672 The software can identify a FREEDM-32A672 attached to an APPI bus by reading the TYPE[3:0] bits in the FREEDM-32A672 Master Reset (0x000) register. The default value of TYPE[3:0] = 0001B indicates that the device is the FREEDM-32A672 member of the FREEDM family of products. For purposes of responding to receive polling and receive device selection, the address space occupied by each FREEDM-32A672 on the receive APPI needs to be configured using the base address bits (BADDR[2:0]) in the RAPI Control (0x580) register. Similarly, for purposes of responding to transmit polling and transmit data transfers, the address space occupied by each FREEDM-32A672 on the transmit APPI needs to be configured using the base address bits (BADDR[2:0]) in the TAPI Control (0x600) register. Note that up to seven FREEDM-32A672 devices may share a single APPI bus (one address is reserved as a null address), with an external controller acting as bus master. In addition, the software can identify the version level of the FREEDM-32A672 with the ID[7:0] bits in the FREEDM-32A672 Master Reset (0x000) register. This may be useful to distinguish between future versions of the FREEDM-32A672. Memory Mapping the Register Space During power-up, the Normal Mode Register space needs to be mapped to the microprocessor. This register space is located in the FREEDM-32A672 and is accessed through the microprocessor interface. All registers are 16 bits wide but are DWORD aligned in the microprocessor memory map.
8.2
Reset This section describes the procedure to reset the FREEDM-32A672 via software. The FREEDM-32A672 is powered on in an inactive state and should be reset via software following a hardware reset, or as required by the embedded processor. The reset procedure is normally followed by the initialization procedure.
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The steps to reset a FREEDM-32A672 are: 1. If the FREEDM-32A672 was active before the reset procedure, then the deactivation procedure must be done (see section 8.6). 2. The RESET bit in the FREEDM-32A672 Master Reset (0x000) register must be written high and then written low. This reset procedure has the following effects: * The RESET bit allows the FREEDM-32A672 to be reset under software control. If the RESET bit is a logic one, the entire FREEDM-32A672 except the microprocessor interface is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the FREEDM-32A672 out of reset. Holding the FREEDM-32A672 in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. All Normal Mode registers are set to their default values. None of the channel provisioning, or the Channel FIFO configuration is preserved under software reset.
* * 8.3
Initialization This section describes the procedure to initialize the FREEDM-32A672. The initialization procedure normally follows the software reset procedure and is followed by the activation procedure. The steps to initialize a FREEDM-32A672 are: 1. Configure the serial links. The register accesses are described in section 5. 2. Assign base addresses for the receive and the transmit APPI. The register accesses are described in sections 6.1 and 6.2. 3. Configure HDLC processing of the RHDL672 and the THDL672 blocks. The register accesses are described in sections 7.1 and 7.2.
8.4
Activation Procedure The activation procedure is required to place the FREEDM-32A672 in a state after which the software may service FREEDM-32A672 interrupts, provision/unprovision channels, and monitor the status of the FREEDM-32A672.
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The activation procedure normally follows the initialization procedure. The steps to activate a FREEDM-32A672 are: 1. Enable interrupt `E' bits as described in section 4. 2. Enable data transfer across the receive and transmit APPI by setting the ENABLE bits to one in the RAPI672 and TAPI672 registers as described in sections 6.1 and 6.2. 3. The SYSCLKA, TDBA, RFP8A, TFP8A, RFPA[3:0], TFPA[3:0], RXCLKA, and TXCLKA bits in the FREEDM-32A672 Master Clock/Frame Pulse/BERT Activity Monitor and Accumulation Trigger (0x00C) register should be read periodically to detect for stuck at conditions. The SYSCLKA bit must be read high for proper operation of the FREEDM-32A672. A low value indicates a failure in clocking that is provided at the SYSCLK input pin of the FREEDM32A672. Similarly, a low value in the other register bits indicates a failure in clocking that is provided by the corresponding input pin. 4. The TLGA[7:0] and the RLGA[7:0] bits in the FREEDM-32A672 Master Link Activity Monitor (0x010) register should be read periodically to detect for stuck at conditions. The bits which correspond to links attached to the FREEDM-32A672 should be read high. A low value indicates a failure in clocking that is provided by the corresponding RCLK[n:m], RMVCK[n], 1 RMV8DC, TCLK[n:m], TMVCK[n], or TMV8DC input pins. 8.5 Deactivation Procedure The deactivation procedure is required to place the FREEDM-32A672 in a state in which it will not interrupt the embedded processor, or transfer data across the APPI. This procedure should occur after the FREEDM-32A672 actively transfers packets, or to gracefully shut down the FREEDM-32A672. The steps to deactivate a FREEDM-32A672 are: 1. Disable interrupt `E' bits as described in section 4. 2. Disable data transfer across the receive and transfer APPI by programming the ENABLE bits to zero in the RAPI672 and TAPI672 registers as described in sections 6.1 and 6.2.
1
Each RLGA[7:0] or TLGA[7:0] bit corresponds to a group of 4 non H-MVIP links (in addition to the H-MVIP links). If less than four links are configured, then the unused RCLK or TCLK inputs should be tied to the same clock as one of the configured links in this group.
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3. Continue by performing the software reset procedure. 8.6 Provisioning a Channel The provisioning procedure normally follows the activation procedure and enables the FREEDM-32A672 to receive and/or transmit packets. 8.6.1 Receive Channel Provisioning The steps to provision a receive channel RCC, where 0 RCC 671 are: 1. Disable FREEDM-32A672 processing of the channel's data stream to allow for graceful provisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Register RCAS Channel Disable (0x10C) RCAS Channel Disable (0x10C) Value
RCC
1
2. Program the Channel FIFO as described in section 7.3.1. 3. Poll the BUSY bit of the RHDL Indirect Channel Select (0x200) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 4. Specify the HDLC configuration for this channel by writing appropriate bits in the RHDL Indirect Channel Data Register #1 (0x204) and the RHDL Indirect Channel Data Register #2 (0x208) as described in section 7.4. When writing the RHDL Indirect Channel Data Register #1, ensure that the PROV bit is set, and ensure that the FPTR[10:0] bits identify a block within the circular linked list of buffers of step 2. 5. Specify the RHDL672 channel to provision by writing the following register. Then poll the BUSY bit to ensure that it is low before proceeding to step 6. Bit CHAN[9:0] CRWB BUSY Register RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) Value
RCC
0 X
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6. Poll the BUSY bit of the RCAS Indirect Link and Time-slot Select (0x100) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 7. Specify the RCAS672 channel that is provisioned. Write the following register: Bit CHAN[9:0] PROV CDLBEN Register RCAS Indirect Channel Data (0x104) RCAS Indirect Channel Data (0x104) RCAS Indirect Channel Data (0x104) Value
RCC
1 0
8. For a channelised link, specify the time-slots which are assigned for processing on this channel by writing the following register once for each time-slot that is assigned to the channel. Valid values for TSLOT[4:0] are 1 through 24 for a T1/J1 link, 1 through 31 for an E1 link, and 0 through 31 for an H-MVIP link. For an unchannelised link, TSLOT[4:0] must only have the value 0, and this register is written just once. Each write must be followed by a read to determine whether the BUSY bit (bit15) is low, and to ensure that the indirect RAM has been updated. Bit TSLOT[4:0] LINK[4:0] Reserved[1:0] RWB BUSY Register RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) Value see above 0 through 31 are valid 00 0 X
9. Enable FREEDM-32A672 processing of the channel data stream to allow for graceful provisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Register RCAS Channel Disable (0x10C) RCAS Channel Disable (0x10C) Value
RCC
0
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Warning: * The RCAS Channel Disable bit (CHDIS) is only applicable to one channel at a time. In other words, the receive channel provisioning procedure needs to be run once for each channel. The programmer must ensure that the channel has not been provisioned, or has been unprovisioned before doing the provisioning procedure. The reset procedure has the effect of unprovisioning all channels of the FREEDM32A672. Continuous polling of a register in a tight loop involves multiple microprocessor memory read transactions and may have an adverse effect on the microprocessor bus bandwidth available for other activities. The recommended method of polling the BUSY bit is to read the register on expiration of a system timer, or after a number of CPU clock ticks. Recommended time intervals are in the range 0.1 msec through 1 msec. A Channel is not provisioned until the BUSY bit toggles low.
*
*
*
8.6.2 Transmit Channel Provisioning The steps to provision a transmit channel TCC, where 0 TCC 671 are: 1. Disable FREEDM-32A672 processing of the channel's data stream to allow for graceful provisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Register TCAS Channel Disable (0x410) TCAS Channel Disable (0x410) Value
TCC
1
2. Program the Channel FIFO as described in section 7.3.2 for a transmit channel. 3. Poll the BUSY bit of the THDL Indirect Channel Select (0x380) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 4. Specify the HDLC configuration for this transmit channel by writing the THDL Indirect Channel Data Register #1 (0x384), THDL Indirect Channel Data Register #2 (0x388) and the THDL Indirect Channel Data Register #3 (0x38C) as described in section 7.5. In writing the THDL Indirect Channel
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Data Register #1, ensure the PROV bit is set, and ensure the FPTR[10:0] bits identify a block within the circular linked list of buffers of step 2. 5. Specify the THDL672 channel that is provisioned by writing the following register. Then poll the BUSY bit to ensure it is low before proceeding with step 6. Bit CHAN[9:0] CRWB BUSY Register THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) Value
TCC
0 X
6. Poll the BUSY bit of the TCAS Indirect Link and Time-slot Select (0x400) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 7. Specify the TCAS672 channel that is provisioned. Write the following register: Bit CHAN[9:0] PROV Register TCAS Indirect Channel Data (0x404) TCAS Indirect Channel Data (0x404) Value
TCC
1
8. For a channelised link, specify the time-slots which are assigned for processing on this channel by writing the following register once for each time-slot that is assigned to the channel. Valid values for TSLOT[4:0] are 1 through 24 for a T1/J1 link, 1 through 31 for an E1 link, and 0 through 31 for an H-MVIP link. For an unchannelised link, TSLOT[4:0] must only have the value 0, and this register is written just once. Each write must be followed by a read to determine whether the BUSY bit (bit15) is low, and to ensure that the indirect RAM has been updated. Bit TSLOT[4:0] LINK[4:0] Reserved[1:0] RWB Register TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) Value see above 0 through 31 are valid 00 0
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Bit BUSY
Register TCAS Indirect Link and Time-slot Select (0x400)
Value X
9. Poll the BUSY bit of the TAPI Indirect Channel Provisioning (0x604) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 10. Specify the channel burst length and enable channel provisioning by writing the following register. The BLEN[7:0] bits need to be set according to the XFER[3:0] value of the THDL672 as described in section 6.2. Bit BLEN[7:0] PROV Register TAPI Indirect Channel Data Register (0x608) TAPI Indirect Channel Data Register (0x608) Value see above 1
11. Specify the TAPI672 channel to provision. Write the following register fields, then poll the BUSY bit to ensure that the provisioning process has completed. Bit CHAN[9:0] RWB BUSY Register TAPI Indirect Channel Provisioning (0x604) TAPI Indirect Channel Provisioning (0x604) TAPI Indirect Channel Provisioning (0x604) Value
TCC
0 X
12. Enable FREEDM-32A672 processing of the channel data stream to allow for graceful provisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Warning: * The TCAS Channel Disable bit (CHDIS) is only applicable to one channel at a time. In other words, the transmit channel provisioning procedure needs to be run once for each channel. The programmer must ensure that the channel has not been provisioned, or has been unprovisioned before doing the provisioning procedure. The reset Register TCAS Channel Disable (0x410) TCAS Channel Disable (0x410) Value
TCC
0
*
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PM7381 FREEDM-32A672
PROGRAMMER'S GUIDE
procedure has the affect of unprovisioning all channels of the FREEDM32A672. * Continuous polling of a register in a tight loop involves multiple microprocessor memory read transactions and may have an adverse effect on the microprocessor bus bandwidth available for other activities. The recommended method of polling the BUSY bit is to read the register on expiration of a system timer, or after a number of CPU clock ticks. Recommended time intervals are in the range 0.1 msec through 1 msec. A Channel is not provisioned until the BUSY bit toggles low.
* 8.7
Unprovisioning a Channel The unprovisioning procedure is normally applied to channels that are provisioned.
8.7.1 Receive Channel Unprovisioning The steps to unprovision a receive channel RCC, where 0 RCC 671 are: 1. Disable FREEDM-32A672 processing of the channel's data stream to allow for graceful unprovisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Register RCAS Channel Disable (0x10C) RCAS Channel Disable (0x10C) Value
RCC
1
2. Poll the BUSY bit of the RCAS Indirect Link and Time-slot Select (0x100) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 3. Specify the RCAS672 channel to unprovision by writing the following register: Bit CHAN[9:0] PROV CDLBEN Register RCAS Indirect Channel Data (0x104) RCAS Indirect Channel Data (0x104) RCAS Indirect Channel Data (0x104) Value
RCC
0 X
4. For a channelised link, specify the time-slots which are unassigned on this channel by writing the following register once for each time-slot that is
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PM7381 FREEDM-32A672
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unassigned. Valid values for TSLOT[4:0] are 1 through 24 for a T1/J1 link, 1 through 31 for an E1 link, and 0 through 31 for an H-MVIP link. For an unchannelised link, TSLOT[4:0] must only have the value 0, and this register is written just once. Each write must be followed by a read to determine whether the BUSY bit (bit15) is low, and to ensure that the indirect RAM has been updated. Bit TSLOT[4:0] LINK[4:0] Reserved[1:0] RWB BUSY Register RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) Value see above 0 through 31 are valid 00 0 X
5. Poll the BUSY bit of the RHDL Indirect Channel Select (0x200) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 6. Read the RHDL672 channel data by writing the following register. Then poll the BUSY bit to ensure it is low before proceeding with step 7. Bit CHAN[9:0] CRWB BUSY Register RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) Value
RCC
1 X
7. Read the RHDL672 indirect channel data and check that the TAVAIL bit of the RHDL Indirect Channel Data #1 (0x204) register is zero. This ensures that the last data transfer across the receive APPI for this channel has completed. If the TAVAIL bit is zero, proceed to step 8, otherwise, return to step 6. 8. Write the RHDL Indirect Channel Data #1 (0x204) register with PROV modified to zero, while keeping the same FPTR[10:0] bits.
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PM7381 FREEDM-32A672
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9. Specify the RHDL672 channel to unprovision by writing the following register. Then poll the BUSY bit to ensure that it is low before proceeding with step 10. Bit CHAN[9:0] CRWB BUSY Register RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) Value
RCC
0 X
10. Enable FREEDM-32A672 processing of the unprovisioned channel. Write the following bits: Bit DCHAN[9:0] CHDIS Warning: * The RCAS Channel Disable bit (CHDIS) is only applicable to one channel at a time. In other words, the receive channel unprovisioning procedure needs to be run once for each channel. Continuous polling of a register in a tight loop involves multiple microprocessor memory read transactions and may have an adverse effect on the microprocessor bus bandwidth available for other activities. The recommended method of polling the BUSY bit is to read the register on expiration of a system timer, or after a number of CPU clock ticks. Recommended time intervals are in the range 0.1 msec through 1 msec. A Channel is not unprovisioned until the BUSY bit toggles low. Register RCAS Channel Disable (0x10C) RCAS Channel Disable (0x10C) Value
RCC
0
*
*
8.7.2 Transmit Channel Unprovisioning The steps to unprovision a transmit channel TCC, where 0 TCC 671 are: 1. Poll the BUSY bit of the TAPI Indirect Channel Provisioning (0x604) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 2. Enable channel unprovisioning by writing the following register:
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PM7381 FREEDM-32A672
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Bit PROV
Register TAPI Indirect Channel Data Register (0x608)
Value 0
3. Specify the TAPI672 channel to unprovision. Write the following register fields, then poll the BUSY bit to ensure that the unprovisioning process has completed. Bit CHAN[9:0] RWB BUSY Register TAPI Indirect Channel Provisioning (0x604) TAPI Indirect Channel Provisioning (0x604) TAPI Indirect Channel Provisioning (0x604) Value
TCC
0 X
4. Disable FREEDM-32A672 processing of the channel's data stream to allow for graceful unprovisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Register TCAS Channel Disable (0x410) TCAS Channel Disable (0x410) Value
TCC
1
5. Poll the BUSY bit of the TCAS Indirect Link and Time-slot Select (0x400) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 6. Specify the TCAS672 channel to be unprovisioned. Write the following register: Bit CHAN[9:0] PROV Register TCAS Indirect Channel Data (0x404) TCAS Indirect Channel Data (0x404) Value
TCC
0
7. For a channelised link, specify the time-slots which are unassigned for processing on this channel by writing the following register once for each time-slot that is unassigned. Valid values for TSLOT[4:0] are 1 through 24 for a T1/J1 link, 1 through 31 for an E1 link, and 0 through 31 for an H-MVIP link. For an unchannelised link, TSLOT[4:0] must only have the value 0, and this register is written just once. Each write must be followed by a read to determine whether the BUSY bit (bit15) is low, and to ensure that the indirect RAM has been updated.
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PM7381 FREEDM-32A672
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Bit TSLOT[4:0] LINK[4:0] Reserved[1:0] RWB BUSY
Register TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400)
Value see above 0 through 31 are valid 00 0 X
8. Poll the BUSY bit of the THDL Indirect Channel Select (0x380) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 9. Read the THDL672 channel data by writing the following register. Then poll the BUSY bit to ensure that it is low before proceeding with step 9. Bit CHAN[9:0] CRWB BUSY Register THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) Value
TCC
1 X
10. Read the THDL Indirect Channel Data #1 (0x384) register. Then write this register with PROV modified to zero, while keeping the same FPTR[10:0] bits. 11. Specify the THDL672 channel to unprovision by writing the following register. Then poll the BUSY bit to ensure that it is low before proceeding with step 11. Bit CHAN[9:0] CRWB BUSY Register THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) Value
TCC
0 X
12. Enable FREEDM-32A672 processing of the channel. Write the following bits:
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PM7381 FREEDM-32A672
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Bit DCHAN[9:0] CHDIS Warning: *
Register TCAS Channel Disable (0x410) TCAS Channel Disable (0x410)
Value
TCC
0
The TCAS Channel Disable bit (CHDIS) is only applicable to one channel at a time. In other words, the transmit channel unprovisioning procedure needs to be run once for each channel. Continuous polling of a register in a tight loop involves multiple microprocessor memory read transactions and may have an adverse effect on the microprocessor bus bandwidth available for other activities. The recommended method of polling the BUSY bit is to read the register on expiration of a system timer, or after a number of CPU clock ticks. Recommended time intervals are in the range 0.1 msec through 1 msec. A Channel is not unprovisioned until the BUSY bit toggles low.
*
* 8.8
Receive Sequence The software is not required to receive packets when interfacing to the RAPI672. Data transfer functions for the FREEDM-32A672 are performed by an external controller. In the receive direction, the external controller transfers partial packets out of the internal 32 Kbyte partial packet buffer RAM in the RHDL672, across the receive APPI bus, and into host packet memory. Please refer to the Longform Datasheet[1] for detailed information on the operation and timing of the receive APPI.
8.9
Transmit Sequence The software is not required to transmit packets when interfacing to the TAPI672. Data transfer functions for the FREEDM-32A672 are performed by an external controller. In the transmit direction, the external controller provides packets to transmit using the transmit APPI. For each provisioned HDLC channel, an external controller transfers partial packets across the transfer APPI, and into the internal 32 Kbyte partial packet buffer RAM in the THDL672. Please refer to the
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PM7381 FREEDM-32A672
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Longform Datasheet[1] for detailed information on the operation and timing of the transmit APPI. 8.10 Performance Counters The FREEDM-32A672 provides four count registers within the Normal Mode Register Space. These are as follows: Bit OF[15:0] UF[15:0] C1[15:0] C2[15:0] Register PMON Receive FIFO Overflow Count (0x504) PMON Transmit FIFO Underflow Count (0x508) PMON Configurable Count #1 (0x50C) PMON Configurable Count #2 (0x510)
The software must poll these counters to prevent overflow. Figure 15 illustrates the sequence of events when the counters are polled. The PMON Status (0x500) register provides status bits which indicate whether any of the four internal holding counters has overflowed. Figure 15 - Event Sequence for Polling of Counters
Accumulation Period, N-1
Accumulation Period, N Reset Counter Count Events
Accumulation Period, N+1 Reset Counter
Internal Counter
Count Value Transfer
Count Value Transfer
Visible Counter
Delay Reload Counter Read Counter Time (Not to Scale)
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The software initiates a counter reload by writing to the FREEDM-32A672 Master Clock/Frame Pulse/BERT Activity Monitor and Accumulation Trigger (0x00C) register. There is a small delay to transfer data from internal counters to the visible counters. The recommended polling strategy is to read the counters first before initiating a reload. Using this strategy, the transfer latency can be ignored. Counters are normally configured during initialization. The first configurable count register is assigned by setting one of the following register bits, while setting all other bits to zero: Bit RSPE1EN RFCSE1EN RABRT1EN RLENE1EN RP1EN TABRT1EN TP1EN Register FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024)
The second configurable count register is assigned by setting one of the following register bits, while setting all other bits to zero: Bit RSPE2EN RFCSE2EN RABRT2EN Register FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024)
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Bit RLENE2EN RP2EN TABRT2EN TP2EN
Register FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024) FREEDM-32A672 Master Performance Monitor Control (0x024)
8.11 Line Loopback Serial ports configured for non H-MVIP traffic can be placed in line loopback. In this configuration, receive data from the serial link is looped back to the transmit serial link as illustrated in Figure 16. Line loopback is not supported for H-MVIP traffic. Figure 16 - Line Loopback
Tx
Tx Any-PHY Packet Interface (transmit data is dropped before reaching the link) Rx
Serial Link Interface
FREEDM-32A672
Rx
Non H-MVIP serial ports can be placed in line loopback by setting the appropriate bit within one of the following registers. There are 32 bits corresponding to the 32 serial ports. Bit LLBEN[15:0] LLBEN[31:16] Register FREEDM-32A672 Master Line Loopback #1 (0x014) FREEDM-32A672 Master Line Loopback #2 (0x018)
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PM7381 FREEDM-32A672
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Note: The software should unprovision channels associated with the link that is placed in line loopback mode before placing the link in line loopback. This will prevent the data stream at the serial link from passing through the FREEDM32A672 to the receive APPI. 8.12 Diagnostic Loopback Each channel of the FREEDM-32A672 can be placed in a diagnostic loopback mode. In this configuration, the transmit data stream is looped back to the receive data stream as illustrated in Figure 17. The pair of transmit/receive channels is configured in diagnostic loopback mode by provisioning both the transmit and the receive channels as specified in section 8.7, except with the CDLBEN bit set high within the RCAS Indirect Channel Data (0x104) register. In diagnostic loopback mode, the transmit channel data is looped back as well as driven onto the transmit serial link. The channel data from the receive serial link is dropped. The TCLK[n] input pin provides the bit timing for the diagnostic loopback mode. Figure 17 - Diagnostic Loopback
Tx Serial Link Interface (receive channel data is dropped) Rx
Tx
FREEDM-32A672
Any-PHY Packet Interface
Rx
Note: For the diagnostic loopback to pass data through the FREEDM-32A672, the receive line clock must be provided at the RCLK[n] input pin for the link that is placed in diagnostic loopback. The data rate for the diagnostic loopback is the same as the clock rate provided at this pin. 8.13 BERT Port The FREEDM-32A672 provides pins to transmit/receive a BERT data stream on serial links configured for non H-MVIP traffic. The following register is written to
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enable the BERT port and transmit/receive the BERT data stream on serial port n, where 0 n 31. Bit RBSEL[4:0] RBEN TBSEL[4:0] TBEN Register FREEDM-32A672 Master BERT Control (0x020) FREEDM-32A672 Master BERT Control (0x020) FREEDM-32A672 Master BERT Control (0x020) FREEDM-32A672 Master BERT Control (0x020) Value
n
1
n
1
The BERT port is disabled by programming the following register: Bit RBSEL[4:0] RBEN TBSEL[4:0] TBEN Register FREEDM-32A672 Master BERT Control (0x020) FREEDM-32A672 Master BERT Control (0x020) FREEDM-32A672 Master BERT Control (0x020) FREEDM-32A672 Master BERT Control (0x020) Value X 0 X 0
The TDBA bit of the FREEDM-32A672 Master Clock/Frame Pulse/BERT Activity Monitor and Accumulation Trigger (0x00C) can be read by software to determine whether transmit data is present at the BERT port. Note: The FREEDM-32A672 channels which are assigned to the same link as the BERT port should be unprovisioned to prevent the receive BERT data stream from passing through the FREEDM-32A672 to the receive APPI.
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APPENDIX A - REGISTER LEVEL CHANGES The following table is a comparison of the normal mode registers at the register level among the FREEDM-32, the FREEDM-32P672 and the FREEDM-32A672. Registers in bold indicate differences at the register level among the members of the FREEDM family listed in the table. Table entries that are "N/A" indicate that the register is not applicable in the corresponding FREEDM device. Please see Appendix D for differences at the bit level for the normal mode registers.
Register FREEDM-32xxxx Master Reset FREEDM-32xxxx Master Interrupt Enable FREEDM-32xxxx Master Interrupt Status FREEDM-32xxxx Master Clock/Frame Pulse/BERT Activity Monitor and Accumulation Trigger FREEDM-32xxxx Master Link Activity Monitor FREEDM-32xxxx Master Line Loopback #1 FREEDM-32xxxx Master Line Loopback #2 Reserved FREEDM-32xxxx Reserved FREEDM-32xxxx Master BERT Control FREEDM-32xxxx Master Performance Monitor Control
FREEDM-32 FREEDM-32P672 FREEDM-32A672 PCI Offset PCI Offset Address 0x000 0x004 0x008 0x00C 0x000 0x004 0x008 0x00C 0x000 0x004 0x008 0x00C
0x010 0x014 0x018 0x01C N/A 0x020 0x024
0x010 0x014 0x018 N/A 0x01C 0x020 0x024
0x010 0x014 0x018 N/A 0x01C 0x020 0x024
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Register Reserved GPIC Control GPIC Reserved Reserved RCAS Indirect Channel and Time-slot Select RCAS Indirect Channel Data RCAS Framing Bit Threshold RCAS Channel Disable RCAS Reserved RCAS Link #0 through #31 Configuration RHDL Indirect Channel Select RHDL Indirect Channel Data Register #1 RHDL Indirect Channel Data Register #2 RHDL Reserved RHDL Indirect Block Select RHDL Indirect Block Data Register RHDL Reserved RHDL Configuration RHDL Maximum Packet Length
FREEDM-32 FREEDM-32P672 FREEDM-32A672 PCI Offset PCI Offset Address 0x028 - 0x03C 0x040 0x044 - 0x07C 0x080 - 0x0FC 0x100 0x104 0x108 0x10C 0x110 - 0x17C 0x180 - 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 - 0x21C 0x220 0x224 0x028 - 0x07C 0x080 0x084 - 0x0FC N/A 0x100 0x104 0x108 0x10C 0x110 - 0x17C 0x180 - 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 - 0x21C 0x220 0x224 0x028 - 0x0FC N/A N/A N/A 0x100 0x104 0x108 0x10C 0x110 - 0x17C 0x180 - 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 - 0x21C 0x220 0x224
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Register RHDL Reserved Reserved RMAC Control RMAC Indirect Channel Provisioning RMAC Packet Descriptor Table Base LSW RMAC Packet Descriptor Table Base MSW RMAC Queue Base LSW RMAC Queue Base MSW RMAC Packet Descriptor Reference Large Buffer Free Queue Start RMAC Packet Descriptor Reference Large Buffer Free Queue Write RMAC Packet Descriptor Reference Large Buffer Free Queue Read RMAC Packet Descriptor Reference Large Buffer Free Queue End RMAC Packet Descriptor Reference Small Buffer Free Queue Start RMAC Packet Descriptor Reference Small Buffer Free Queue Write
FREEDM-32 FREEDM-32P672 FREEDM-32A672 PCI Offset PCI Offset Address 0x228 - 0x23C 0x240 - 0x27C 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x228 - 0x23C 0x240 - 0x27C 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x228 - 0x23C 0x240 - 0x37C N/A N/A N/A N/A N/A N/A N/A
0x29C
0x29C
N/A
0x2A0
0x2A0
N/A
0x2A4
0x2A4
N/A
0x2A8
0x2A8
N/A
0x2AC
0x2AC
N/A
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Register RMAC Packet Descriptor Reference Small Buffer Free Queue Read RMAC Packet Descriptor Reference Small Buffer Free Queue End RMAC Packet Descriptor Reference Ready Queue Start RMAC Packet Descriptor Reference Ready Queue Write RMAC Packet Descriptor Reference Ready Queue Read RMAC Packet Descriptor Reference Ready Queue End RMAC Reserved TMAC Control TMAC Indirect Channel Provisioning TMAC Descriptor Table Base LSW TMAC Descriptor Table Base MSW TMAC Queue Base LSW TMAC Queue Base MSW TMAC Descriptor Reference Free Queue Start
FREEDM-32 FREEDM-32P672 FREEDM-32A672 PCI Offset PCI Offset Address 0x2B0 0x2B0 N/A
0x2B4
0x2B4
N/A
0x2B8
0x2B8
N/A
0x2BC
0x2BC
N/A
0x2C0
0x2C0
N/A
0x2C4
0x2C4
N/A
0x2C8 - 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318
0x2C8 - 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318
N/A N/A N/A N/A N/A N/A N/A N/A
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Register TMAC Descriptor Reference Free Queue Write TMAC Descriptor Reference Free Queue Read TMAC Descriptor Reference Free Queue End TMAC Descriptor Reference Ready Queue Start TMAC Descriptor Reference Ready Queue Write TMAC Descriptor Reference Ready Queue Read TMAC Descriptor Reference Ready Queue End TMAC Reserved THDL Indirect Channel Select THDL Indirect Channel Data #1 THDL Indirect Channel Data #2 THDL Indirect Channel Data #3 THDL Reserved THDL Indirect Block Select
FREEDM-32 FREEDM-32P672 FREEDM-32A672 PCI Offset PCI Offset Address 0x31C 0x31C N/A
0x320
0x320
N/A
0x324 0x328
0x324 0x328
N/A N/A
0x32C
0x32C
N/A
0x330
0x330
N/A
0x334
0x334
N/A
0x338 - 0x37C 0x380 0x384 0x388 0x38C 0x390 - 0x39C 0x3A0
0x338 - 0x37C 0x380 0x384 0x388 0x38C 0x390 - 0x39C 0x3A0
N/A 0x380 0x384 0x388 0x38C 0x390 - 0x39C 0x3A0
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Register THDL Indirect Block Data THDL Reserved THDL Configuration THDL Reserved Reserved TCAS Indirect Channel and Time-slot Select TCAS Indirect Channel Data TCAS Framing Bit Threshold TCAS Idle Time-slot Fill Data TCAS Channel Disable TCAS Reserved TCAS Link #0 through #31 Configuration PMON Status PMON Receive FIFO Overflow Count PMON Transmit FIFO Underflow Count PMON Configurable Count #1 PMON Configurable Count #2 PMON Reserved Reserved
FREEDM-32 FREEDM-32P672 FREEDM-32A672 PCI Offset PCI Offset Address 0x3A4 0x3A8 - 0x3AC 0x3B0 0x3B4 - 0x3BC 0x3C0 - 0X3FC 0x400 0x404 0x408 0x40C 0x410 0x414 - 0x47C 0x480 - 0x4FC 0x500 0x504 0x508 0x50C 0x510 0x514 - 0x51C 0x520 - 0x7FC 0x3A4 0x3A8 - 0x3AC 0x3B0 0x3B4 - 0x3BC 0x3C0 - 0X3FC 0x400 0x404 0x408 0x40C 0x410 0x414 - 0x47C 0x480 - 0x4FC 0x500 0x504 0x508 0x50C 0x510 0x514 - 0x51C 0x520 - 0x7FC 0x3A4 0x3A8 - 0x3AC 0x3B0 0x3B4 - 0x3BC 0x3C0 - 0X3FC 0x400 0x404 0x408 0x40C 0x410 0x414 - 0x47C 0x480 - 0x4FC 0x500 0x504 0x508 0x50C 0x510 0x514 - 0x51C 0x520 - 0x57C
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Register RAPI Control RAPI Reserved Reserved TAPI Control TAPI Indirect Channel Provisioning TAPI Indirect Channel Data Register TAPI Reserved Reserved
FREEDM-32 FREEDM-32P672 FREEDM-32A672 PCI Offset PCI Offset Address N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x580 0x584 - 0x5BC 0x5C0 - 0x5FC 0x600 0x604 0x608 0x60C - 0x63C 0x640 - 0x7FC
Note: There are no PCI Configuration registers in the FREEDM-32A672 device.
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APPENDIX B - NEW NORMAL MODE REGISTERS The following registers are new for the FREEDM-32A672. The new registers are used to configure and control the new RAPI672 and TAPI672 blocks. Please refer to the Longform Datasheet[1] for detailed descriptions of these registers.
FREEDM-32A672 Address 0x580 0x584 - 0x5BC 0x600 0x604 0x608 0x60C - 0x63C RAPI Control RAPI Reserved TAPI Control
Register
TAPI Indirect Channel Provisioning TAPI Indirect Channel Data Register TAPI Reserved
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APPENDIX C - NON-APPLICABLE NORMAL MODE REGISTERS The following FREEDM-32 registers are no longer applicable for the FREEDM32A672. These registers were used to configure and control the RMAC, TMAC and GPIC of the FREEDM-32.
FREEDM-32 PCI Offset 0x040 0x044 - 0x07C 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 GPIC Control GPIC Reserved RMAC Control
Register
RMAC Indirect Channel Provisioning RMAC Packet Descriptor Table Base LSW RMAC Packet Descriptor Table Base MSW RMAC Queue Base LSW RMAC Queue Base MSW RMAC Packet Descriptor Reference Large Buffer Free Queue Start RMAC Packet Descriptor Reference Large Buffer Free Queue Write RMAC Packet Descriptor Reference Large Buffer Free Queue Read RMAC Packet Descriptor Reference Large Buffer Free Queue End RMAC Packet Descriptor Reference Small Buffer Free Queue Start RMAC Packet Descriptor Reference Small Buffer Free Queue Write RMAC Packet Descriptor Reference Small Buffer Free Queue Read RMAC Packet Descriptor Reference Small Buffer Free Queue End RMAC Packet Descriptor Reference Ready Queue Start
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FREEDM-32 PCI Offset 0x2BC 0x2C0 0x2C4 0x2C8 - 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 - 0x37C
Register RMAC Packet Descriptor Reference Ready Queue Write RMAC Packet Descriptor Reference Ready Queue Read RMAC Packet Descriptor Reference Ready Queue End RMAC Reserved TMAC Control TMAC Indirect Channel Provisioning TMAC Descriptor Table Base LSW TMAC Descriptor Table Base MSW TMAC Queue Base LSW TMAC Queue Base MSW TMAC Descriptor Reference Free Queue Start TMAC Descriptor Reference Free Queue Write TMAC Descriptor Reference Free Queue Read TMAC Descriptor Reference Free Queue End TMAC Descriptor Reference Ready Queue Start TMAC Descriptor Reference Ready Queue Write TMAC Descriptor Reference Ready Queue Read TMAC Descriptor Reference Ready Queue End TMAC Reserved
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APPENDIX D - NORMAL MODE REGISTER BIT CHANGES The following normal mode registers have changed at the bit level from the FREEDM-32 to the FREEDM-32A672. Unless otherwise specified, register names, locations and comments refer to FREEDM-32A672 registers. Register 0x000 : FREEDM-32A672 Master Reset
Bit FREEDM-32A672 Function 15 11 10 9 8 7 6 5 4 3 2 1 0 Reset TYPE[3] TYPE[2] TYPE[1] TYPE[0] ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] Default 0 0 0 0 1 0 0 0 0 0 0 0 0 FREEDM-32 Function Reset Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Default 0 X X X X X X X X X X X X Now also forces the APPI outputs tristate. New Device Type bits allow software to identify the device as the FREEDM-32A672 member of the FREEDM family of products. New Device ID bits allow software to identify the version level of FREEDM32A672. Comments
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Register 0x004 : FREEDM-32A672 Master Interrupt Enable
Bit FREEDM-32A672 Function 14 13 12 11 10 9 8 7 6 1 0 TFOVRE TUNPVE TPRTYE Unused Unused Unused Unused Unused Unused Unused Unused Default 0 0 0 X X X X X X X X FREEDM-32 Function IOCE TDFQEE TDQRDYE TDQFE RPDRQEE RPDFQEE RPQRDYE RPQLFE RPQSFE PERRE SERRE Default 0 0 0 0 0 0 0 0 0 0 0 SERRE, PERRE, IOCE, and all queue-related interrupt enable bits are not used because queues and the PCI bus are not used for the FREEDM32A672. New interrupt enable bits are TPRTYE, TUNPVE, and TFOVRE. Comments
Register 0x008 : FREEDM-32A672 Master Interrupt Status
Bit FREEDM-32A672 Function 14 13 12 11 10 9 8 7 6 1 0 TFOVRI TUNPVI TPRTYI Unused Unused Unused Unused Unused Unused Unused Unused Default 0 0 0 X X X X X X X X FREEDM-32 Function IOCI TDFQEI TDQRDYI TDQFI RPDRQEI RPDFQEI RPQRDYI RPQLFI RPQSFI PERRI SERRI Default 0 0 0 0 0 0 0 0 0 0 0 SERRI, PERRI, IOCI, and all queue-related interrupt status bits are not used because queues and the PCI bus are not used for the FREEDM-32A672. New interrupt status bits are TPRTYI, TUNPVI, and TFOVRI. Comments
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Register 0x00C : FREEDM-32A672 Master Clock / Frame Pulse /BERT Activity Monitor and Accumulation Trigger
Bit FREEDM-32A672 Function 13 12 11 10 9 8 7 6 5 4 3 TXCLKA RXCLKA TFPA[3] TFPA[2] TFPA[1] TFPA[0] RFPA[3] RFPA[2] RFPA[1] RFPA[0] TFP8A Default X X X X X X X X X X X FREEDM-32 Function Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Default X X X X X X X X X X X Transmit 8.192 Mbps H-MVIP frame pulse activity bit. Receive 8.192 Mbps H-MVIP frame pulse activity bit. Receive 2.048 Mbps H-MVIP frame pulse activity bits. Any-PHY transmit clock active bit. Any-PHY receive clock active bit. Transmit 2.048 Mbps H-MVIP frame pulse activity bits. Comments
2
RFP8A
X
Unused
X
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Register 0x010 : FREEDM-32A672 Master Link Activity Monitor
Bit FREEDM-32A672 Function 15 11 10 9 8 7 6 5 4 3 2 1 0 TLGA[7] TLGA[3] TLGA[2] TLGA[1] TLGA[0] RLGA[7] RLGA[6] RLGA[5] RLGA[4] RLGA[3] RLGA[2] RLGA[1] RLGA[0] Default X X X X X X X X X X X X X FREEDM-32 Function TLGA[7] TLGA[3] TLGA[2] TLGA[1] TLGA[0] RLGA[7] RLGA[6] RLGA[5] RLGA[4] RLGA[3] RLGA[2] RLGA[1] RLGA[0] Default X X X X X X X X X X X X X Now also monitors TMV8DC input. Now also monitors TMVCK[3] input. Now also monitors TMVCK[2] input. Now also monitors TMVCK[1] input. Now also monitors TMVCK[0] input. Now also monitors RMVCK[3] and RMV8DC inputs. Now also monitors RMVCK[2] and RMV8DC inputs. Now also monitors RMVCK[1] and RMV8DC inputs. Now also monitors RMVCK[0] and RMV8DC inputs. Comments
Register 0x01C : FREEDM-32A672 Reserved
Bit FREEDM-32A672 Function 0 Reserved Default 0 FREEDM-32 Function Not Specified Default X Reserved bit must be set low for correct operation of FREEDM-32A672. Comments
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Register 0x100 : RCAS Indirect Link and Time-slot Select
Bit FREEDM-32A672 Function 12 11 10 9 8 7 6 Reserved Reserved LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Default 0 0 0 0 0 0 0 FREEDM-32 Function LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Unused Unused Default 0 0 0 0 0 X X Reserved bits must be set low for correct operation of FREEDM-32A672. Comments
Register 0x104 : RCAS Indirect Channel Data
Bit FREEDM-32A672 Function 15 14 9 8 7 CDLBEN PROV CHAN[9] CHAN[8] CHAN[7] Default 0 0 0 0 0 FREEDM-32 Function Unused Unused CDLBEN PROV Unused Default X X 0 0 X Increase in size of CHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments
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Register 0x108 : RCAS Framing Bit Threshold
Bit FREEDM-32A672 Function 6 5 4 3 2 1 0 FTHRES[6] FTHRES[5] FTHRES[4] FTHRES[3] FTHRES[2] FTHRES[1] FTHRES[0] Default 0 1 0 0 1 0 1 FREEDM-32 Function FTHRES[6] FTHRES[5] FTHRES[4] FTHRES[3] FTHRES[2] FTHRES[1] FTHRES[0] Default 0 1 1 1 1 1 1 Change of default value. Change of default value. Change of default value. Comments
Register 0x10C : RCAS Channel Disable
Bit FREEDM-32A672 Function 9 8 7 DCHAN[9] DCHAN[8] DCHAN[7] Default 0 0 0 FREEDM-32 Function Unused Unused Unused Default X X X Increase in size of DCHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments
Registers 0x180 - 0x188 : RCAS Links #0 to #2 Configuration
Bit FREEDM-32A672 Function 4 2 1 0 BSYNC MODE[2] MODE[1] MODE[0] Default 0 0 0 0 FREEDM-32 Function Unused BSYNC E1 CEN Default X 0 0 0 New mode select bits; see table below. E1 is no longer used. CEN is no longer used. Comments
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Registers 0x18C - 0x1FC : RCAS Links #3 to #31 Configuration
Bit FREEDM-32A672 Function 2 1 0 MODE[2] MODE[1] MODE[0] Default 0 0 0 FREEDM-32 Function Unused E1 CEN Default X 0 0 New mode select bits; see table below. E1 is no longer used. CEN is no longer used. Comments
The mode select bits are encoded as follows to configure the serial links of the FREEDM-32A672: MODE[2:0] Link Configuration 000 Unchannelised 001 Channelised T1/J1 (24 time slots labeled 1-24) 010 Channelised E1 (31 time slots labeled 1-31) 011 2 Mbps H-MVIP (32 time slots labeled 0-31) 100 Reserved 101 Reserved 110 Reserved 111 8 Mbps H-MVIP (128 time slots mapped to timeslots 0 through 31 of links 4m, 4m+1, 4m+2 and 4m+3) Register 0x200 : RHDL Indirect Channel Select
Bit FREEDM-32A672 Function 9 8 7 CHAN[9] CHAN[8] CHAN[7] Default 0 0 0 FREEDM-32 Function Unused Unused Unused Default X X X Increase in size of CHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments
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Register 0x204 : RHDL Indirect Channel Data #1
Bit FREEDM-32A672 Function 14 STRIP Default 0 FREEDM-32 Function CRC[1] Default 0 CRC[1] moved to bit 11 of Register 0x208 of the FREEDM-32A672. CRC[0] moved to bit 10 of Register 0x208 the FREEDM-32A672. Comments
13
DELIN
0
CRC[0]
0
12 11
TAVAIL Reserved
X X
STRIP DELIN
0 0 Reserved bit must be set low for correct operation of the FREEDM-32A672. Increase in size of FPTR from 9 bits to 11 bits as the result of increase in addressable descriptors from 512 to 2048.
10 9
FPTR[10] FPTR[9]
X X
TAVAIL Unused
X X
Register 0x208 : RHDL Indirect Channel Data #2
Bit FREEDM-32A672 Function 11 CRC[1] Default 0 FREEDM-32 Function Unused Default X CRC[1] moved from bit 14 of Register 0x204 of the FREEDM-32. CRC[0] moved from bit 13 of Register 0x204 of the FREEDM-32. XFER increased from 3 bits to 4 bits to support larger data transfers. Comments
10
CRC[0]
0
Unused
X
3
XFER[3]
0
Unused
X
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Register 0x210 : RHDL Indirect Block Select
Bit FREEDM-32A672 Function 11 Reserved Default X FREEDM-32 Function Unused Default X Reserved bit must be set low for correct operation of FREEDM-32A672. BLOCK increased from 9 bits to 11 bits as the result of increase in addressable blocks from 512 to 2048. Comments
10 9
BLOCK[10] BLOCK[9]
X X
Unused Unused
X X
Register 0x214 : RHDL Indirect Block Data
Bit FREEDM-32A672 Function 11 Reserved Default X FREEDM-32 Function Unused Default X Reserved bit must be set low for correct operation of FREEDM-32A672. BPTR increased from 9 bits to 11 bits as a result of increase in addressable blocks from 512 to 2048. Comments
10 9
BPTR[10] BPTR[9]
X X
Unused Unused
X X
Register 0x220 : RHDL Configuration
Bit FREEDM-32A672 Function 2 1 0 Unused Unused Unused Default X X X FREEDM-32 Function Reserved[2] Reserved[1] Reserved[0] Default 1 1 1 These reserved bits are no longer used in the FREEDM-32A672. Comments
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Register 0x380 : THDL Indirect Channel Select
Bit FREEDM-32A672 Function 9 8 7 CHAN[9] CHAN[8] CHAN[7] Default 0 0 0 FREEDM-32 Function Unused Unused Unused Default X X X Increase in size of CHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments
Register 0x384 : THDL Indirect Channel Data #1
Bit FREEDM-32A672 Function 12 DELIN Default X FREEDM-32 Function IDLE Default 0 IDLE moved to bit 14 of Register 0x38C of the FREEDM-32A672. Reserved bit must be set low for correct operation of FREEDM-32A672. Increase in size of FPTR from 9 bits to 11 bits as the result of increase in addressable descriptors from 512 to 2048. Comments
11
Reserved
X
DELIN
0
10 9
FPTR[10] FPTR[9]
0 0
Unused Unused
X X
Register 0x388 : THDL Indirect Channel Data #2
Bit FREEDM-32A672 Function 14 11 Reserved Reserved Default 0 0 FREEDM-32 Function PRIORITYB Unused Default 0 X Reserved bits must be set low for correct operation of FREEDM-32A672. PRIORITYB is not used. 10 9 FLEN[10] FLEN[9] 0 0 Unused Unused X X Increase in size of FLEN from 9 bits to 11 bits as the result of increase in addressable descriptors from 512 to 2048. Comments
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Register 0x38C : THDL Indirect Channel Data #3
Bit FREEDM-32A672 Function 14 IDLE Default 0 FREEDM-32 Function Unused Default X IDLE moved from bit 12 of Register 0x384 of the FREEDM-32. XFER increased from 3 bits to 4 bits to support larger data transfers. Comments
3
XFER[3]
0
Unused
X
Register 0x3A0 : THDL Indirect Block Select
Bit FREEDM-32A672 Function 11 Reserved Default X FREEDM-32 Function Unused Default X Reserved bit must be set low for correct operation of FREEDM-32A672. BLOCK increased from 9 bits to 11 bits as the result of increase in addressable blocks from 512 to 2048. Comments
10 9
BLOCK[10] BLOCK[9]
0 0
Unused Unused
X X
Register 0x3A4 : THDL Indirect Block Data
Bit FREEDM-32A672 Function 11 Reserved Default X FREEDM-32 Function Unused Default X Reserved bit must be set low for correct operation of FREEDM-32A672. BPTR increased from 9 bits to 11 bits as the result of increase in addressable blocks from 512 to 2048. Comments
10 9
BPTR[10] BPTR[9]
0 0
Unused Unused
X X
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Register 0x3B0 : THDL Configuration
Bit FREEDM-32A672 Function 7 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 FREEDM-32 Function BURSTEN Unused BURST[2] BURST[1] BURST[0] Default 0 X 0 0 0 Reserved bits must be set low for correct operation of FREEDM-32A672. The DMA burst length feature is not used. Comments
Register 0x400 : TCAS Indirect Link and Time-slot Select
Bit FREEDM-32A672 Function 12 11 10 9 8 7 6 Reserved Reserved LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Default 0 0 0 0 0 0 0 FREEDM-32 Function LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Unused Unused Default 0 0 0 0 0 X X Reserved bits must be set low for correct operation of the FREEDM-32A672. Comments
Register 0x404 : TCAS Indirect Channel Data
Bit FREEDM-32A672 Function 15 9 8 7 PROV CHAN[9] CHAN[8] CHAN[7] Default 0 0 0 0 FREEDM-32 Function Unused Unused PROV Unused Default X X 0 X Increase in size of CHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments
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Register 0x408 : TCAS Framing Bit Threshold
Bit FREEDM-32A672 Function 6 5 4 3 2 1 0 FTHRES[6] FTHRES[5] FTHRES[4] FTHRES[3] FTHRES[2] FTHRES[1] FTHRES[0] Default 0 1 0 0 1 0 1 FREEDM-32 Function FTHRES[6] FTHRES[5] FTHRES[4] FTHRES[3] FTHRES[2] FTHRES[1] FTHRES[0] Default 0 0 1 1 1 1 1 Change of default value. Change of default value. Change of default value. Change of default value. Comments
Register 0x410 : TCAS Channel Disable
Bit FREEDM-32A672 Function 9 8 7 DCHAN[9] DCHAN[8] DCHAN[7] Default 0 0 0 FREEDM-32 Function Unused Unused Unused Default X X X Increase in size of DCHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments
Registers 0x480 - 0x488 : TCAS Links #0 to #2 Configuration
Bit FREEDM-32A672 Function 4 2 1 0 BSYNC MODE[2] MODE[1] MODE[0] Default 0 0 0 0 FREEDM-32 Function Unused BSYNC E1 CEN Default X 0 0 0 New mode select bits; see table below. E1 is no longer used. CEN is no longer used. Comments
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Registers 0x48C - 0x4FC : TCAS Links #3 to #31 Configuration
Bit FREEDM-32A672 Function 2 1 0 MODE[2] MODE[1] MODE[0] Default 0 0 0 FREEDM-32 Function Unused E1 CEN Default X 0 0 New mode select bits; see table below. E1 is no longer used. CEN is no longer used. Comments
The mode select bits are encoded as follows to configure the serial links of the FREEDM-32A672: MODE[2:0] Link Configuration 000 Unchannelised 001 Channelised T1/J1 (24 time slots labeled 1-24) 010 Channelised E1 (31 time slots labeled 1-31) 011 2 Mbps H-MVIP (32 time slots labeled 0-31) 100 Reserved 101 Reserved 110 Reserved 111 8 Mbps H-MVIP (128 time slots mapped to timeslots 0 through 31 of links 4m, 4m+1, 4m+2 and 4m+3)
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
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None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-990639 (A1) date: June 1999
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